E T H E R N E T C O M M U N I C A T I O N M O D U L E

 

 

Transmit packet processor

 

The TX_WR logic examines the status received from the MAC after it has transmitted

 

 

the frame.

Frame

If the frame was transmitted successfully, the TX_WR logic sets TXDONE (frame

transmitted

transmission complete) in the Ethernet Interrupt Status register and reads the next

successfully

buffer descriptor. If a new frame is available (that is, the F bit is set), the TX_WR

 

 

starts transferring the frame. If a new frame is not available, the TX_WR logic sets

 

the TXIDLE (TX_WR logic has no frame to transmit) bit in the Ethernet Interrupt

 

Status register and waits for the software to toggle TCLER (clear transmit logic), in

 

Ethernet General Control Register #2, from low to high to resume processing. When

 

TCLER is toggled, transmission starts again with the buffer descriptor pointed to by

 

the Transmit Recover Buffer Descriptor Pointer register. Software should update this

 

register before toggling TCLER.

Frame

If the TX_WR logic detects that the frame was aborted or had an error, the logic

transmitted

updates the current buffer descriptor as described in the previous paragraph. If the

unsuccessfully

frame was aborted before the last buffer descriptor of the frame was accessed, the

 

 

result is a situation in which the status field of a buffer descriptor, which is not the

 

last buffer descriptor in a frame, has a non-zero value. The TX_WR logic stops

 

processing frames until TCLER (clear transmit logic) in Ethernet General Control

 

Register #2 is toggled from low to high to resume processing. The TX_WR logic also

 

sets TXERR (last frame not transmitted successfully) in the Ethernet Interrupt Status

 

register and loads the TX buffer descriptor RAM address of the current buffer

 

descriptor in the TX Error Buffer Descriptor Pointer register (see page 320). This

 

allows identification of the frame that was not transmitted successfully. As part of

 

the recovery procedure, software must read the TX Error Buffer Descriptor Pointer

 

register and then write the 8-bit address of the buffer descriptor to resume

 

transmission into the TX Recover Buffer Descriptor Pointer register.

Transmitting a frame to the Ethernet MAC

Ethernet underrun

The TX_RD logic is responsible for reading data from the TX_FIFO and sending it to the Ethernet MAC. The logic does not begin reading a new frame until the TX_FIFO is full. This scheme decouples the data transfer to the Ethernet MAC from the fill rate from the AHB bus. For short frames that are less than 256 bytes, the transmit process begins when the end-of-frame signal is received from the TX_WR logic.

When the MAC completes a frame transmission, it returns status bits that are stored in the Ethernet Transmit Status register (see page 283) and written into the status field of the current buffer descriptor.

An Ethernet underrun can only occur due to the following programming errors:

–Insufficient bandwidth is assigned to the Ethernet transmitter.

272Hardware Reference NS9215

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Digi NS9215 Frame, Transmitted, Successfully, Unsuccessfully, Transmitting a frame to the Ethernet MAC Ethernet underrun
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NS9215 specifications

The Digi NS9215 is a powerful solution designed for industrial applications that require reliable connectivity and robust performance. Built on a foundation of advanced technologies, the NS9215 serves as a versatile networking device that meets the demands of automation, remote monitoring, and data acquisition.

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