Digi NS9215 manual A c h e L o c k d o w n r e g i s t e r, Modified virtual address format MVA

Modified virtual address format (MVA)

WO R K I N G W I T H T H E C P U

R9: Cache Lockdown register

Operation	Data	Instruction
Invalidate set-associative TLB	SBZ	MCR p15, 0, Rd, c8, c6, 0
Invalidate single entry	MVA	MCR p15, 0, Rd, c8, c6, 1

The invalidate TLB operations invalidate all the unpreserved entries in the TLB.

The invalidate TLB single entry operations invalidate any TLB entry corresponding to the modified virtual address given in Rd, regardless of its preserved state. See "R10:TLB Lockdown register," beginning on page 101, for an explanation of how to preserve TLB entries.

This is the modified virtual address format used for invalid TLB single entry operations.

31	10	9	0
Modified virtual address			SBZ

Note: If either small or large pages are used, and these pages contain subpage access permissions that are different, you must use four invalidate TLB single entry operations, with the MVA set to each subpage, to invalidate all information related to that page held in a TLB.

R 9 : C a c h e L o c k d o w n r e g i s t e r

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Register R9 access the cache lockdown registers. Access this register using CRm = 0.

Cache ways	The Cache Lockdown register uses a cache-way-based locking scheme (format C)
	that allows you to control each cache way independently.
	These registers allow you to control which cache-ways of the four-way cache are
	used for the allocation on a linefill. When the registers are defined, subsequent
	linefills are placed only in the specified target cache way. This gives you some
	control over the cache pollution cause by particular applications, and provides a
	traditional lockdown operation for locking critical code into the cache.
	A locking bit for each cache way determines whether the normal cache allocation is
	allowed to access that cache way (see “Cache Lockdown register L bits” on
	page 99). A maximum of three cache ways of the four-way associative cache can be
	locked, ensuring that normal cache line replacement is performed.
	Note: If no cache ways have the L bit set to 0, cache way 3 is used for all linefills.

98Hardware Reference NS9215