I 2 C M A S T E R / S L A V E I N T E R F A C E

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Physical I2C bus. .

I2C Master/Slave Interface

C H A P T E R

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The I2C master/slave interface provides an interface between the ARM CPU and

 

the I2C bus.

 

The I2C master/slave interface basically is a parallel-to-serial and serial-to-parallel

 

converter. The parallel data received from the ARM CPU has to be converted to an

 

appropriate serial form to be transmitted to an external component using the I2C

 

bus. Similarly, the serial data received from the I2C bus has to be converted to an

 

appropriate parallel form for the ARM CPU. The I2C master interface also manages

 

the interface timing, data structure, and error handling.

Overview

The I2C module is designed to be a master and slave. The slave is active only when

 

the module is being addressed during an I2C bus transfer; the master can arbitrate

 

for and access the I2C bus only when the bus is free (idle) — therefore, the master

 

and slave are mutually exclusive.

P h y s i c a l I 2 C b u s

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The physical I2C bus consists of two open-drain signal lines: serial data (SDA) and serial clock (SCL). Pullup resistors are required; see the standard I2C bus specification for the correct value for the application. Each device connected to the bus is software-addressable by a unique 7- or 10-bit address, and a simple master/slave relationship exists at all times.

A master can operate as a master-transmitter (writes)) or a master-receiver (reads). The slaves respond to the received commands accordingly:

In transmit mode (slave is read), the host interface receives character-based

parallel data from the ARM. The module converts the parallel data to serial format and transmits the serial data to the I2C bus.

In receive mode (slave is written to), the I2C bus interface receives 8-bit- based serial data from the I2C bus. The module converts the serial data to

parallel format and interrupts the host. The host’s interrupt service routine reads the parallel data from the data register inside the I2C module. The serial data stream synchronization and throttling are done by modulating the

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Digi NS9215 manual Y s i c a l I 2 C b u s, I2C bus, Interface timing, data structure, and error handling, Overview

NS9215 specifications

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