Digi NS9215 manual H e r n e t R e c e i v e S t a t u s r e g i s t e r, Address A060 001C

E T H E R N E T C O M M U N I C A T I O N M O D U L E

Ethernet Receive Status register

Bits	Access	Mnemonic	Reset	Description
D08	R	TXAJ	0x0	TX abort — jumbo
				When set, indicates that the frame’s length exceeded
				the value set in the Maximum Frame register. TXAJ is
				set only if the HUGE bit in MAC Configuration
				Register #2 is set to 0.
				Jumbo frames result in the TX buffer descriptor buffer
				length field being set to 0x000.
				If the HUGE bit is set to 0, the frame is truncated. If
				TXAJ is set, the TX_WR logic stops processing frames
				and sets the TXERR bit in the Ethernet Interrupt Status
				register.
D07	R	Not used	0x0	Always set to 0.
D06	R	TXDEF	0x0	Transmit frame deferred
				When set, indicates that the frame was deferred for at
				least one attempt, but less than the maximum number
				for an excessive deferral. TXDEF is also set when a
				frame was deferred due to a collision.
				This bit is not set for late collisions.
D05	R	TXCRC	0x0	Transmit CRC error
				When set, indicates that the attached CRC in the frame
				did not match the internally-generated CRC. This bit is
				not set if the MAC is inserting the CRC in the frame
				(that is, the CRCEN bit is set in MAC Configuration
				Register #2). If TXCRC is set, the TX_WR logic stops
				processing frames and sets the TXERR bit in the
				Ethernet Interrupt Status register.
D04	R	Not used	0x0	Always set to 0.
D03:00	R	TXCOLC	0x0	Transmit collision count
				Number of collisions the frame incurred during
				transmission attempts.

E t h e r n e t R e c e i v e S t a t u s r e g i s t e r

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Address: A060 001C

The Ethernet Receive Status register contains the status for the last completed receive frame. The RXBR bit in the Ethernet Interrupt Status register (see page 317) is set whenever a receive frame is completed and the Ethernet Receive Status register is loaded at the same time. Bits [15:0] are also loaded into the status field of the receive buffer descriptor used for the frame.

286Hardware Reference NS9215