R E A L TI M E C L O C K M O D U L E

Interrupt Enable register

I n t e r r u p t E n a b l e r e g i s t e r

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Address: 9006 0020

The Interrupt Enable register sets which events can generate and interrupt. The interrupt that is generated remains set until it is cleared by disabling the event or by reading/clearing the Event Flags register.

Register

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

Alrm

Mnth

Date

Hour

Min

Sec

Hsec

 

 

 

 

 

 

 

 

Int

Int

Int

Int

Int

Int

Int

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register bit

assignment

Bits

Access

Mnemonic

Reset

Description

 

 

 

 

 

 

 

 

D31:07

N/A

Reserved

N/A

N/A

 

 

 

 

 

 

 

 

D06

W

Alrm Int

0x0

Alarm interrupt

 

 

 

 

 

0

Disable alarm interrupt

 

 

 

 

 

1

Enable alarm interrupt

 

 

 

 

 

 

 

D05

W

Mnth Int

0x0

Month interrupt

 

 

 

 

 

0

Disable month interrupt

 

 

 

 

 

1

Enable month interrupt

 

 

 

 

 

 

 

D04

W

Date Int

0x0

Date interrupt

 

 

 

 

 

0

Disable date interrupt

 

 

 

 

 

1

Enable date interrupt

 

 

 

 

 

 

 

D03

W

Hour Int

0x0

Hour interrupt

 

 

 

 

 

0

Disable hour interrupt

 

 

 

 

 

1

Enable hour interrupt

 

 

 

 

 

 

 

D02

W

Min Int

0x0

Minute interrupt

 

 

 

 

 

0

Disable minute interrupt

 

 

 

 

 

1

Enable minute interrupt

 

 

 

 

 

 

 

D01

W

Sec Int

0x0

Second interrupt

 

 

 

 

 

0

Disable second interrupt

 

 

 

 

 

1

Enable second interrupt

 

 

 

 

 

 

 

D00

W

Hsec Int

0x0

Hundredth of a second interrupt

 

 

 

 

 

0

Disable hundredth second interrupt

 

 

 

 

 

1

Enable hundredth second interrupt

 

 

 

 

 

 

 

468Hardware Reference NS9215

Page 467 Page 469
Page 468
Image 468
Digi NS9215 manual Alarm interrupt, Month interrupt, Date interrupt, Hour interrupt, Minute interrupt, Second interrupt
Page 467 Page 469

NS9215 specifications

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