I 2 C M A S T E R / S L A V E I N T E R F A C E

Configuration register

C o n f i g u r a t i o n r e g i s t e r

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Address: 9005 000C

The Configuration register controls the timing on the I2C bus. This register also controls the external interrupt indication, which can be disabled.

The I2C bus clock timing is programmable by the scl_ref value (D08:00). The timing parameter for standard mode is as follows:

I2C_bus_clock = clk / ((CLREF*2) + 4 + scl_delay) clk = PLL Clk Out/4

Notes: To determine the “PLL Clk Out” frequency, see the “PLL configuration and control system block diagram” on page 152 and the “PLL Configuration register” on page 186. In noisy environments and fast-mode transmission, spike filtering can be applied to the received I2C data and clock signal. The spike filter evaluates the incoming signal and suppresses spikes. The maximum length of the suppressed spikes can be specified in the spike filter width field of the Configuration register.

Timing parameter for fast-mode

Register

This is the timing parameter for fast-mode:

I2C_bus_clock = (4 / 3) x (clk / ((CLREF*2) + 4 + scl_delay)) scl_delay is influenced by the SCL rise time.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

s

 

 

 

 

 

 

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IRQD

TMDE

VSCD

 

 

SFW

 

 

 

 

 

CLREF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register bit assignment

Bits

Access

Mnemonic

Reset

Description

D31:16

N/A

Reserved

N/A

N/A

 

 

 

 

 

D15

R/W

IRQD

0

Mask the interrupt to the ARM CPU (irq_dis)

 

 

 

 

Must be set to 0.

 

 

 

 

 

D14

R/W

TMDE

1

Timing characteristics of serial data and serial

 

 

 

 

clock

 

 

 

 

0Standard mode

 

 

 

 

1Fast mode

 

 

 

 

 

D13

R/W

VSCD

1

Virtual system clock divider for master and

 

 

 

 

slave

 

 

 

 

Must be set to 0.

454Hardware Reference NS9215

Page 454
Image 454
Digi NS9215 manual Address 9005 000C, Timing parameter for fast-mode Register, Mask the interrupt to the ARM CPU irqdis

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