Digi NS9215 manual Instruction or data lockdown register, Access, Instructions

Instruction or data lockdown register

WO R K I N G W I T H T H E C P U	. .
R9: Cache Lockdown register..
	.

The first four bits of this register determine the L bit for the associated cache way. The opcode_2 field of the MRC or MCR instruction determines whether the instruction or data lockdown register is accessed:

opcode_2=0	Selects the DCache Lockdown register, or the Unified
	Cache Lockdown register if a unified cache is
	implemented. The ARM926EJ-S processor has separate
	DCache and ICache.
opcode_2=1	Selects the ICache Lockdown register.

Access	Use these instructions to access the CacheLockdown register.
instructions
	Function	Data	Instruction
	Read DCache Lockdown register	L bits	MRC p15, 0, Rd, c9, c0, 0
	Write DCache Lockdown register	L bits	MCR p15, 0, Rd, c9, c0, 0
	Read ICache Lockdown register	L bits	MRC p15, 0, Rd, c9, c0, 1
	Write ICache Lockdown register	L bits	MCR p15, 0, Rd, c9, c0, 1

Modifying the Cache Lockdown register

Register format

You must modify the Cache Lockdown register using a modify-read-write sequence; for example:

MRC p15, 0, Rn, c9, c0, 1;

ORR Rn, Rn, 0x01;

MCR p15, 0, Rn, c9, c0, 1;

This sequence sets the L bit to 1 for way 0 of the ICache.

This is the format for the Cache Lockdown register.

31	16	15	4	3	0
SBZ/UNP		SB0			L bits
					(cache ways
					0 to 3)

Cache Lockdown register L bits

This table shows the format of the Cache Lockdown register L bits. All cache ways are available for allocation from reset.

Bits	4-way associative	Notes
[31:16]	UNP/SBZ	Reserved
[15:4]	0xFFF	SBO

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