Digi NS9215 manual A t i s t i c s m o d u l e, MAC receiver

E T H E R N E T C O M M U N I C A T I O N M O D U L E

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	Statistics module.
	.
	module. The filtering options, listed next, are programmed in the Station Address
	Filter register (see page 301).
	Accept frames to destination address programmed in the SA1, SA2, and SA3
	registers (Station Address registers, beginning on page 300)
	Accept all frames
	Accept all multicast frames
	Accept all multicast frames using HT1 and HT2 registers. See “Sample hash
	table code,” on page 334)
	Accept all broadcast frames
	The filtering conditions are independent of each other; for example, the Station
	Address Logic register can be configured to accept all broadcast frames, and frames
	to the programmed destination address.
MAC receiver	The MAC receiver provides the station address logic with a 6-bit CRC value that
	is the upper 6 bits of a 32-bit CRC calculation performed on the 48-bit
	multicast destination address. This 6-bit value addresses the 64-bit multicast
	hash table created in the HT1 and HT2 registers. See “Sample hash table
	code,” on page 334)
	If the current receive frame is a multicast frame and the 6-bit CRC addresses a
	bit in the hash table that is set to 1, the receive frame is accepted; otherwise,
	the frame is rejected. See “Sample hash table code,” on page 334) for sample
	C code to calculate hash table entries.

S t a t i s t i c s m o d u l e

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The Statistics module counts and saves Ethernet statistics in several counters (see “Statistics registers” on page 303).

The Ethernet General Control Register #2 contains three statistics module configuration bits:

AUTOZ. Enable statistics counter clear on read. CLRCNT. Clear statistics counters.

STEN. Enable statistics counters.

If any of the counters roll over, an associated carry bit is set in the Carry 1 (CAR1) or Carry 2 (CAR2) registers (see "General Statistics registers address map," beginning on page 310). Any statistics counter overflow can cause the STOVFL bit in the Ethernet Interrupt Status register (see page 317) to be set if its associated mask bit is not set in Carry Mask Register 1 or Carry Mask Register 2.

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