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Digi NS9215 manual Manufacturer Part Number Description, NC7SP17, 74LVC1G17GW, SN74LVC1G17DC

Models: NS9215

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T I M I N G

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Reset and edge sensitive input timing requirements. .

If an external device driving the reset or edge sensitive input on a Digi processor cannot meet the 500ns maximum rise and fall time requirement, the signal must be buffered with a Schmitt trigger device. Here are sample Schmitt trigger device part numbers:

Manufacturer	Part Number	Description

Fairchild	NC7SP17	Single Schmitt trigger buffer,
		available in 5-lead SC70 and 6-lead MicroPak packages

Philips	74LVC1G17GW	Single Schmitt trigger buffer,
		available in 5-lead SC70 and SOT 353 packages

TI	SN74LVC1G17DC	Single Schmitt trigger buffer,
		available in 5-lead SC70 and SOT 353 packages

ON Semi	NL17SZ17DFT2	Single Schmitt trigger buffer,
		available in 5-lead SC70 and SOT 353 packages.

www.digiembedded.com

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Digi NS9215 manual Manufacturer Part Number Description, NC7SP17, 74LVC1G17GW, SN74LVC1G17DC, NL17SZ17DFT2

Contents

90000847C Release date 10 April NS9215 Hardware ReferencePage Page Page Contents A p t e r 3 W o r k i n g w i t h t h e C P U 102 105 A p t e r 4 S y s t e m C o n t r o l M o d u l e 137 141 A p t e r 5 M e m o r y C o n t r o l l e r 203 Sram Bit wide configuration 228 229 Hardware Reference NS9215 HT1 315 A p t e r 7 E x t e r n a l D M a 339 Hardware Reference NS9215 A p t e r 9 I / O H u b M o d u l e 363 Hardware Reference NS9215 A p t e r 1 1 S e r i a l C o n t r o l D u l e H D L C 415 Hardware Reference NS9215 A p t e r 1 4 R e a l T i m e C l o c k M o d u l e 459 A p t e r 1 6 T i m i n g 479 A p t e r 1 7 P a c k a g i n g 513 Hardware Reference NS9215 Heading Description PinoutM o r y b u s i n t e r f a c e Pin Signal DescriptionN O U T 2 6 Sdram CAS Pin SignalH e r n e t i n t e r f a c e M a C Sdram RASN e r a l p u r p o s e I / O G P I O RXD Uart a DCD Uart aCTS Uart a DSR Uart aPicdbgdataini DCD / TXC Uart CCTS Uart C I2C SCLRXD Uart B DCD Uart BCTS Uart B DSR Uart BTXC / DTR Uart D DSR Uart DRXD Uart D RI Uart DPin Signal Description PIC1CLKO PIC1CLKIPin Signal Description PIC0CLKO PIC0CLKIPin Signal Description Pin Signal Description Pin Signal Description I/O OD S t e m c l o c kSystem clock drawing S t e m m o d e RTC clock and battery backup drawingSysmode2 Sysmode1 Sysmode0 Description SPI YES S t e m r e s e tA G T e s t Adcvss POR VSS R a n d b a t t e r y b a c k e d l o g i cGND W e r a n d g r o u n dPower and ground Register address Map Address Description Access Reset valueN t r o l a n d S t a t u s r e g i s t e r s System memory bus I/O controlControl and Status registers Gpio configuration options I O C o n f i g u r a t i o n r e g i s t e r sBits Mnemonic Description Address A0902000 Configuration Register #0Configuration Register #1 Bits Access Mnemonic Reset DescriptionAddress A090200C Configuration Register #2Configuration Register #3 Address A0902008Address A0902014 Configuration Register #4Configuration Register #5 Address A0902010Address A090201C Configuration Register #6Configuration Register #7 Address A0902018Address A0902024 Configuration Register #8Configuration Register #9 Address A0902020Address A090202C Configuration Register #10Configuration Register #11 Address A0902028Address A0902034 Configuration Register #12Configuration Register #13 Address A0902030Address A090203C Configuration Register #14Configuration Register #15 Address A0902038Address A0902044 Configuration Register #16Configuration Register #17 Address A0902040Address A090204C Configuration Register #18Configuration Register #19 Address A0902048Address A0902054 Configuration Register #20Configuration Register #21 Address A0902050Address A090205C Configuration Register #22Configuration Register #23 Address A0902058GPIOAddress A0902064 Configuration Register #24Configuration Register #25 Address A0902060Address A0902068 Configuration Register #26I O C o n t r o l r e g i s t e r s Gpio ControlAddress A090206C Address A0902070 Address A0902074 Address A0902078 I O S t a t u s r e g i s t e r s Gpio StatusAddress A0902080 Address A0902084 M o r y B u s C o n f i g u r a t i o n r e g i s t e r Address A0902088Address A090208C CS3 CS0CS1 CS2High data bus pullup control Apudis Memory Bus Configuration register About the processor Working with the CPUARM instruction set Thumb instruction set Process block DiagramS t r u c t i o n s e t s Arm926EJ-SAccessing CP15 registers Java instruction setARM926EJ-S system addresses Address manipulation example For reads Terms and abbreviationsMnemonics for these instructions are Term Abbreviation DescriptionTLB Be ZERO, does not cause any physical damage to the chipRegister summary Register Reads WritesAny value other than 1 or 2. Note this example This is the contents of the ID code registerWriting to register R0 is Unpredictable R0 ID codeField Description Cache type register and field descriptionDsize and Isize fields Field contains these bitsLen field Cache line length O n t r o l r e g i s t e rSize field Cache size Assoc field AssociativityControl register Bit functionalityBits Name Function Behavior ICacheDCache behavior CacheO m a i n a c c e s s C o n t r o l r e g i s t e r CRm and opcode2 fields should be Zero when writing to R2Access permissions and instructions R a n s l a t i o n T a b l e B a s e r e g i s t e rRegister bits Fault S t a t u s r e g i s t e r sAccess instructions E g i s t e rFault a d d r e s s r e g i s t e r Status and domain fieldsPriority Source Size Status Domain Function Description A c h e O p e r a t i o n s r e g i s t e rCache operation functions Function/operation Data format InstructionMVA Modified virtual address format MVA Set/Way format Set/Way example Test and clean DCache instructionsOperation Data Instruction Test, clean, and invalidate DCache instructionL B O p e r a t i o n s r e g i s t e r UnpredictableThat allows you to control each cache way independently A c h e L o c k d o w n r e g i s t e rModified virtual address format MVA Cache waysModifying the Cache Lockdown register Register format AccessInstruction or data lockdown register InstructionsFor each of the cache lines to be locked down in cache way Which region the TLB entry is placed Cache unlock procedure0 T L B L o c k d o w n r e g i s t e r BitUse these instructions to program the TLB Lockdown register 1 a n d R 1 2 r e g i s t e r s3 P r o c e s s I D r e g i s t e r Programming instructions Sample code sequenceFunction Data ARM instruction Fcse PID register Access instructionsPerforming a fast context switch Register format This is the format of the Fcse PID register5 T e s t a n d d e b u g r e g i s t e r Context ID register Access instructionsAccessing reading or writing this register is reserved 4 r e g i s t e rProtection scheme MMU FeaturesM o r y M a n a g e m e n t U n i t M M U State space servo controlAccess permissions and domains Translated entries Register Bits Description MMU program accessible registers Address translationTTB register Format Translation table baseFirst-level fetch Table walk processFirst-level fetch concatenation and address First-level descriptorTable descriptors Section descriptor Format Bits Section Coarse Fine DescriptionValue Meaning Description Bits Description Section descriptor Bit descriptionFine page table Descriptor113 Second-level descriptor pages Second-level descriptor Second-level descriptor formatSecond-level descriptor bit assignments Second-level descriptor least significant bitsBits Large Small Tiny Description Translation sequence for large page references Translating sequence for small page references More information Translation Sequence for tinyReferences Level descriptorU Fault s a n d C P U a b o r t s Transfers Priority encoding table Fault Address register FARDomain Fault Address register FAR values for Multi-wordM a i n a c c e s s c o n t r o l Compatibility issuesSpecifying access permissions Interpreting access permission bitsPrivileged permissions User permissions Fault c h e c k i n g s e q u e n c eNo access 00 Reserved Check domain status Fault checking sequence T e r n a l a b o r t s A b l i n g a n d d i s a b l i n g t h e M M UEnabling Disabling B s t r u c t u r eC h e s a n d w r i t e b u f f e r Cache featuresWrite buffer Enabling the caches DCache Bit settingsSettings R1 register C and M bits for DCacheDescription ARM926EJ-S behavior Table C Table B Bit C h e M V a a n d S e t / W a y f o r m a t sGeneric, virtually indexed, virtually addressed cache Cache format ARM926EJ-SSelf-modifying code N c a c h a b l e i n s t r u c t i o n f e t c h e sThis figure For example, with a 4-way cache a =AHB behavior Instruction Memory Barrier Sample IMB sequences Noncachable instruction fetches S i n t e r c o n n e c t i o n FeaturesS t e m b u s a r b i t e r Locked bus sequence Relinquishing the bus OwnershipUntil the transaction completes Master will not occupy the system busSplit transfers Arbiter configuration example Address range Size System functions D r e s s d e c o d i n gSoftware watchdog timer O g r a m m a b l e t i m e r sMaster Name Hmaster30 assignment Gptc characteristics Control field N e r a l p u r p o s e t i m e r s / c o u n t e r sSource clock frequency S i c P W M f u n c t i o n Bit mode optionsH a n c e d P W M f u n c t i o n A d r a t u r e d e code r f u n c t i o nSample enhanced PWM waveform CCW Input signalsNC No change CW Clockwise CCW Counter clockwise Err Error Quadrature Encoding truthDigital filter Testing signalsTimer support Monitors how far the encoder has moved Typical applicationVector T e r r u p t c o n t r o l l e rFIQ interrupts IRQ interruptsIRQ FIQ IRQ characteristics Interrupt sourcesInterrupt ID Interrupt source Interrupt sources are assigned as shownL c o n f i g u r a t i o n N f i g u r a b l e s y s t e m a t t r i b u t e sPLL configuration and control system block diagram Configuring the powerup settingsO t s t r a p i n i t i a l i z a t i o n Pin name Configuration bits Offset 3124 2316 158 S t e m c o n f i g u r a t i o n r e g i s t e r s155 Isaddr System Memory Chip Select 0 Dynamic Memory Mask Register N e r a l a r b i t e r C o n t r o l r e g i s t e rC 0 , B R C 1 , B R C 2 , a n d B R C 3 r e g i s t e r s Address A090This is how the channels are assigned in the four registers B Error D e t e c t S t a t u sChannel enable bit Channel allocation Register Register bit assignmentEDS1 Address A090 001CTransaction type write or read Not reset CPU instruction errorNot reset CPU data error Not reset AHB error responseEIC AHB Error Interrupt ClearAHB Slave Error Response Detect Config M e r M a s t e r C o n t r o l r e g i s t e rTimer 8 reload step enable Timer 9 reload step enableTimer 9 low step enable Timer 9 high step enableAddresses A090 0190 / 0194 / 0198 / 019C / 01A0 M e r 0 4 C o n t r o l r e g i s t e r sTimer clock select Timer enableCapture and compare mode functions Debug modeAddress A090 01A4 M e r 5 C o n t r o l r e g i s t e rTM2 Reload modeAddresses A090 01A8 / 01AC / 01B0 / 01B4 M e r 6 9 C o n t r o l r e g i s t e r sD3118 Reserved D1716 M e r 6 9 H i g h r e g i s t e r s M e r 6 9 L o w r e g i s t e r s High step M e r 6 9 H i g h a n d L o w S t e p r e g i s t e r sM e r 6 9 R e l o a d S t e p r e g i s t e r s High step directionReload step Reload step directionM e r 0 9 R e a d a n d C a p t u r e r e g i s t e r Individual register mapping Interrupt Vector Address registerRegister 3124 2316 1508 0700 Interrupt type Interrupt enableA D D R r e g i s t e r InvertISA Interrupt service routine addressT e r r u p t S t a t u s a c t i v e Interrupt status activeIsraw T e r r u p t S t a t u s R a wF t w a r e W a t c h d o g C o n f i g u r a t i o n Address A090 016CSoftware watchdog interrupt clear Software watchdog enableSoftware watchdog timer clock select F t w a r e W a t c h d o g T i m e rWatchdog timer O c k C o n f i g u r a t i o n r e g i s t e rAddress A090 017C Memory clock out Clock scale controlMax clock scale control CPU clock selectD u l e R e s e t r e g i s t e r IO hubEthernet MAC I2C Module Reset register resets each module on the AHB busReset status RST StatMiscellaneous System Configuration and Status register Internal register access mode bit Boot modeEndian mode Misaligned bus address response modeL C o n f i g u r a t i o n r e g i s t e r PLL frequency formula Register Register bit assignmentPLL bypass Interrupt ID W e r M a n a g e m e n tAddress A090 018C IntidSdram self refresh control Deprecated Chip sleep enableNew designs should not use this bit Hardware clock scale controlSPI wakeup CPU wake interrupt clearRTC wakeup I2C wakeupB B u s a c t i v i t y S t a t u s Address A090 022CAddresses A090 01D0 / 01D4 Chip select 0 base Chip select 0 disableRegisters Addresses A090 01D8 / 01DCChip select 1disable Addresses A090 01E0 / 01E4Chip select 1 base Chip select 2 disable Addresses A090 01E8 / 01ECChip select 2 base Chip select 3 disable Addresses A090 01F0 / 01F4Chip select 3 base Chip select 0 mask Addresses A09001F8 / 01FCAddresses A090 0200 Chip select 1 disableAddresses A090 0208 / 020C N I D r e g i s t e r CLR GenidSTS StatusPolarity RTC standby mode statusC M o d u l e C o n t r o l r e g i s t e r RTC Module Control register controls the RTC moduleRTC clock ready interrupt clear RTC standby modeRTC clock ready interrupt status RTC module interrupt statusRTC Module Control register Amba 32-bit AHB compliancy Memory controller provides these featuresWith and without asynchronous page mode Static memory features, such asW p o w e r o p e r a t i o n M o r y m a p Power-on reset memory mapExample Boot from flash Sdram remapped after boot Sram Device Write protect Mode BufferA t i c m e m o r y c o n t r o l l e r ROMBe aware Write protection Extended wait transfersAccess sequencing and memory width Wait state generation A t i c m e m o r y i n i t i a l i z a t i o nMemory mapped peripherals ROM, SRAM, and Flash Programmable enableOutput enable programmable delay A t i c m e m o r y r e a d c o n t r o lWAITRD2 WAITOEN0 WAITPAGEN/A WAITWRN/A External memory read transfer with zero wait statesExternal memory read transfer with two wait states Timing parameter ValueWAITENN/A WAITTURNN/A External memory read transfers with zero wait statesBurst of two wait states with fixed length Burst of zero wait states with fixed lengthY n c h r o n o u s p a g e m o d e r e a d External memory page mode read transferWAITRD0 WAITOEN0 WAITPAGE0 WAITWRN/A WAITWENN/A WAITTURNN/A External memory 32-bit burst read from 8-bit memoryWAITRD2 WAITOEN0 WAITPAGE1 WAITWRN/A WAITWENN/A WAITTURNN/A Timing parameters ValueExternal memory write transfer with zero wait states Write enable programming delayA t i c m e m o r y w r i t e c o n t r o l Wait states added between external read and write transfersExternal memory write transfer with two wait states WAITRDN/A WAITOENN/A WAITPAGEN/A WAITWR0 WAITWEN0 WAITTURN0 WAITRD0 WAITOEN0 WAITPAGEN/A WAITWR0 WAITWEN0 WAITTURN0 S t u r n a r o u n dS t u r n a r o u n d T i m i n g a n d p a r a m e t e r s Read followed by write with no turnaroundRead followed by a write with two turnaround cycles Write followed by a read with no turnaroundWAITRD0 WAITOEN0 WAITPAGEN/A WAITWR0 WAITWEN0 WAITTURN2 T e l a n e c o n t r o lD r e s s c o n n e c t i v i t y Memory banks constructed from 16-bit memory Memory banks constructed from 16-or 32-bit memory devices2Mx32 ROM Access sequencing and memory width N a m i c m e m o r y c o n t r o l l e rR a M I n i t i a l i z a t i o n Device size Configuration Load Mode register left shift Left-shift value -bit wide data bus Sdram RBCBit Parameter Parameter description 256M 8M x 16M x 32M x 512M 64M x Left-shift value -bit wide data bus Sdram BRC Bit wide ConfigurationSignal 16M device 64M device 128M 256M 512M Device SignalBA1 BA0Address Register Description G i s t e r sRegister map Only. Bursting is not allowedTRWL, tRDL Reset values N t r o l r e g i s t e rAddress A070 Address mirror Bits Access Mnemonic DescriptionLow-power mode Memory controller enableWrite buffer status A t u s r e g i s t e rN f i g u r a t i o n r e g i s t e r Self-refresh acknowledge SrefackEND N a m i c M e m o r y C o n t r o l r e g i s t e rSelf-refresh request Srefreq Sync/Flash reset/power down signal dypwrnDynamic memory clock enable Sdram initializationRefresh Refresh timerRead data strategy Precharge command period tRP Active to precharge command period tRASRAS Address A070 003C SrexSelf-refresh exit time tSREX APR Last-data-out to active command time tAPRDAL Data-in to active command tDAL or tAPWAddress A070 004C Active to active command period tRCAuto-refresh period and auto-refresh to active command RFCPeriod XSR Exit self-refresh to active time commandMRD Load mode register to Active Command TimeRRD Active Bank a to Active Bank BAddress A070 0100 / 0120 / 0140 External wait timeoutA t i c M e m o r y E x t e n d e d W a i t r e g i s t e r ExampleAM1 Write protectBdmc Address mapping119 Description Memory ConfigurationAddress mapping For the DynamicFor a chip select connected to Select this mapping Address A070 0104 / 0124 / 0144Do not modify RAS latency active to read/write delayCAS CAS latencyExtended wait Buffer enablePsmc BsmcByte lane state Chip select polarityMode Burst mode BmodeMemory width Wwen Wait write enable WaitwenWait output enable Waitoen Address A070 0208 / 0228 / 0248Wtrd Nonpage mode read wait states or asynchronous page modeRead first access wait state Waitrd A t i c M e m o r y R e a d D e l a y 0 3 r e g i s t e r sWtpg Asynchronous page mode read after the first wait stateAddress A070 0218 / 0238 / 0258 WtwrWrite wait states Waitwr Bus turnaround cycles Waitturn WttnStaticMemory Turn Round Delay 0-3 registers Ethernet Communication Module Features Common acronymsEthernet communications module H e r n e t M a CFeature Description MAC module block diagram FeaturesMedia Independent Interface A t i o n a d d r e s s l o g i c S a LPHY interface mappings Station address logicMAC receiver A t i s t i c s m o d u l eH e r n e t f r o n t e n d m o d u l e Ethernet front- end module EFEReceive packet processor Transmit packet processor C e i v e p a c k e t p r o c e s s o rTransferring a frame to system memory Receive buffer descriptor formatReceive buffer descriptor format description Receive buffer descriptor field definitions A n s m i t p a c k e t p r o c e s s o rTransmit buffer descriptor format Transmit buffer Descriptor fieldDefinitions Transmitting a frame Unsuccessfully FrameTransmitted SuccessfullyH e r n e t s l a v e i n t e r f a c e T e r r u p t sInterrupt condition Description Bit field Register Active Default Modules reset State S e t sStatus bits Multicast address filtering example L t i c a s t a d d r e s s f i l t e r i n gFilter entries Multicast address Filter registersWriting to other registers O c k s y n c h r o n i z a t i o nMulticast address Filtering exampleRegister address Filter Txptr RxdptrEintr EintrenAddress A060 H e r n e t G e n e r a l C o n t r o l R e g i s t e r #Accept short 64 receive frames Enable RX packet processingEnable receive DMA Enable TX packet processingErxinit Enable transmit DMAEnable initialization of RX buffer descriptors EtxdmaInsert transmit source address MAC host interface soft resetRX Fifo RAM access Align RX dataH e r n e t G e n e r a l S t a t u s r e g i s t e r H e r n e t T r a n s m i t S t a t u s r e g i s t e r RxinitRX initialization complete TX abort late collision Frame transmitted OKBroadcast frame transmitted Multicast frame transmittedAddress A060 001C H e r n e t R e c e i v e S t a t u s r e g i s t e rReceive multicast frame Receive frame size in bytesReceive frame OK Receive broadcast frameC C o n f i g u r a t i o n R e g i s t e r # Excess deferral Receive enableBits Access Mnemonic Reset Definition Internal loopbackCRC enable Auto detect pad enableVlan pad enable Pad/CRC enableType C k t o B a c k I n t e r P a c k e t G a p r e g i s t e rPAD operation Table for transmit FramesBack-to-back inter-packet-gap Full-duplex modeHalf-duplex mode Address A060 040CNon back-to-back inter-packet-gap part L l i s i o n W i n d o w / R e t r y r e g i s t e rAddress A060 IPGR1Retx X i m u m F r a m e r e g i s t e rCwin Collision windowReset MII management block Maximum frame lengthRmiim Suppress preamble Clocks field SettingsI M a n a g e m e n t C o m m a n d r e g i s t e r Clock selectAutomatically scan for read data I M a n a g e m e n t a d d r e s s r e g i s t e rRegister bit If both Scan and Read are set, Scan takes precedenceI M a n a g e m e n t W r i t e D a t a r e g i s t e r I M a n a g e m e n t R e a d D a t a r e g i s t e rAddress A060 042C MII link failure I M a n a g e m e n t I n d i c a t o r s r e g i s t e rMII read data MiilfAutomatically scan for read data in progress A t i o n a d d r e s s r e g i s t e r sRead data not valid NvalidStation Address Register #2 A t i o n a d d r e s s F i l t e r r e g i s t e rRegister bit assignments for all three registers Station Address Register #1PRA G i s t e r H a s h T a b l e sPRO PRMA t i s t i c s r e g i s t e r s Address Register Transmit and receive countersTR1K Address Register Receive counters Receive statistics Counters addressReceive byte counter A060 069C Receive packet counter A060 06A0Rbuo Receive FCS error counter A060 06A4Receive multicast packet counter A060 06A8 Receive broadcast packet counter A060 06ACReceive undersize packet counter A060 06CC Receive alignment error counter A060 06BCReceive code error counter A060 06C4 Receive carrier sense error counter A060 06C8Address Register Transmit counters Receive jabber counter A060 06D8Transmit statistics counters address map Transmit byte counter A060 06E0Transmit packet counter A060 06E4 Transmit excessive collision packet counter A060 Carry Register Transmit oversize frame counter A060Transmit undersize frame counter A060 These are the General Statistics registersC1RPK C1MAXC1MGV C1RBYMask register M1RFC M1MGVM1RBY M1RPKMask register Register Address A060 073CAddress A060 0A04 0x00000000 RXA Buffer Descriptor PointerRXB Buffer Descriptor Pointer RXD Buffer Descriptor Pointer Address A060 0A08Address A060 0A0C RXC Buffer Descriptor PointerRxbufc H e r n e t I n t e r r u p t S t a t u s r e g i s t e rAddress A060 0A10 RxovflstatRxnobuf RxdonebRxdonec RxdonedAddress A060 0A14 H e r n e t I n t e r r u p t E n a b l e r e g i s t e rAddress A060 0A18 Address A060 0A20 Address A060 0A1CAddress A060 0A24 Address A060 0A28 Address A060 0A30 Address A060 0A2CAddress A060 0A38 Address A060 0A34Rxfreec F r e e B u f f e r r e g i s t e rAddress A060 0A3C RxfreedL t i c a s t a d d r e s s F i l t e r r e g i s t e r s Address A060 0A64 Address A060 0A58Address A060 0A5C Address A060 0A60L t i c a s t a d d r e s s M a s k r e g i s t e r s Address A060 0A9C Address A060 0A90Address A060 0A94 Address A060 0A98Address A060 0AC0 Address A060 0AB4Address A060 0AB8 Address A060 0ABCOffset+0 B u f f e r D e s c r i p t o r R a MAddress A060 2000 512 locations Offset+4Offset+8 Offset+CM p l e h a s h t a b l e code Pointer to buffer to store hash table Pointer to hash table 337 Sample hash table code A t r a n s f e r s External DMADestination DMA buffer descriptor diagramA b u f f e r d e s c r i p t o r Source address pointer Buffer lengthS c r i p t o r l i s t p r o c e s s i n g Variable Definition Use this equation to compute total access timeR i p h e r a l D M a r e a d a c c e s s Determining the width of Pden Equation variablesPeripheral DMA single read access Peripheral DMA burst read accessR i p h e r a l D M a w r i t e a c c e s s Logic remains paused until the REQ signal is reasserted Peripheral DMA burst write accessREQ signal REQ signalRegister name Field Value Comment Done signal Special circumstancesStatic ram chip select configuration A t i c R a M c h i p s e l e c t c o n f i g u r a t i o nA B u f f e r D e s c r i p t o r P o i n t e r A C o n t r o l r e g i s t e r Destination width Channel enableChannel go Source widthFly-by mode Destination burstSource address increment Reset StateIndex Channel abort interrupt pending Error completion interrupt pendingNormal completion interrupt pending Buffer not ready interrupt pendingA P e r i p h e r a l C h i p S e l e c t r e g i s t e r Chip select SELDMA Peripheral Chip Select register Supports ECB, CBC, OFB, CTR, and CCM cipher modes AESProcesses 32 bits at a time Is programmable for 128-, 192-, or 256-bit key lengthsData blocks Block diagramKey size Characteristic 128 192 256 S D M a b u f f e r d e s c r i p t o rDestination buffer length AES buffer descriptor diagramSource address pointer Source buffer lengthInterrupt I bit Last L bit Full F bit AES op codeB p r o c e s s i n g C r y p t i o nCCM mode does not require an initialization vector C , C F B , O F B , a n d C T R p r o c e s s i n gM m o d e Contents Nonce bufferBits CCM mode Hub Module Servicing RX and FIFOs A c o n t r o l l e rAHB slave InterfaceControl12 F Source address pointer Buffer length Control15 WControl14 Control13 LStatus150 Control110Pointer and Index A n s m i t D M a e x a m p l eNot applicable ProcessSystem Memory Visual exampleRegister Offset Description ReservedUart a register Address map Uart B register Address mapUart D register Address map Uart C register Address mapI2C register Address map SPI register Address mapAD register Address map ReservedRTC register Address map IO Hardware Assist registerIO register Address map Channel abort interrupt pending RX Error completion interrupt pending RXNormal completion interrupt pending RX Buffer not ready interrupt pending RXRX Fifo overflow interrupt pending RX Fifo service request interrupt pendingError completion interrupt pending TX TX Fifo service request interrupt pendingD u l e D M a R X C o n t r o l Channel abort Flex I/ODirect Rxbdp RxthrsRX Fifo threshold D u l e D i r e c t M o d e R X S t a t u s F I F O Full flag D u l e D i r e c t M o d e R X D a t a F I F OIndexen D u l e D M a T X C o n t r o lTxbdp TX Fifo threshold D u l e D i r e c t M o d e T X D a t a F I F OD u l e D i r e c t M o d e T X D a t a L a s t F I F O TXDTxdl 384 DMA transfers to and from system memory Modem control signal supportReceive error conditions Character gap timeoutControl register Field Value Comment Example configurationR m a l m o d e o p e r a t i o n Uart module structureDivisor Baud rate U d r a t e g e n e r a t o rBaud rates This table shows the baud rates achieved with CLKref set toR c e d c h a r a c t e r t r a n s m i s s i o n R d w a r e b a s e d f l o w c o n t r o lM w a k e u p o n c h a r a c t e r r e c o g n i t i o n Force character transmission procedure Collecting feedbackDLAB=1 A p p e r C o n t r o l a n d S t a t u s r e g i s t e r sAddress Register DLAB=0Dtren A p p e r C o n f i g u r a t i o n r e g i s t e rRtsen RTSRTS control SoftwareReceive character-based flow control Remote loopbackRS485 transceiver assertion control Enable force completeT e r r u p t E n a b l e r e g i s t e r RS485 transceiver deassertion controlEnable line break Enable overflow errorEnable parity error Enable frame errorT e r r u p t S t a t u s r e g i s t e r Force complete Parity errorFrame error Uart interruptCharacter match1 Ring indicatorCharacter match3 Character match2Write this field to Enable receive character gap timerTransmit idle Receive idleC e i v e B u f f e r G a P C o n t r o l r e g i s t e r Enable transmit bit rate generationEnable character match MaskData FLOW4 Flow control enableFlowstate Flow control stateFLOW2 Char Force transmit enableM W a k e u p C o n t r o l r e g i s t e r Read-only busyTxcount EnableA n s m i t B y t e C o u n t Address 90011034 / 90019034 / 90021034R T R e c e i v e B u f f e r R T T r a n s m i t B u f f e rRbuff Brdl R T B a u d R a t e D i v i s o r L S BR T B a u d R a t e D i v i s o r M S B TbuffEdssi Enables modem status interruptR T I n t e r r u p t E n a b l e r e g i s t e r BrdmInterrupt identification Enables receive line status interruptEnables transmit holding register empty interrupt Enables receive data available interruptClear all bytes in the TX Fifo Enable the TX and RX FifoR T F I F O C o n t r o l r e g i s t e r R T L i n e C o n t r o l r e g i s t e rStick parity, operates as follows Divisor latch access bitParity enable Set break, if set TX data is set toAutomatic flow control Local loopback enable bitR T M o d e m C o n t r o l r e g i s t e r R T L i n e S t a t u s r e g i s t e rR T M o d e m S t a t u s r e g i s t e r Delta CTS indicator Delta DCD indicatorTrailing edge of RI indicator Delta DSR indicatorUart Modem Status register Hdlc module structure C e i v e a n d t r a n s m i t o p e r a t i o n sTransmitter underflow O c k i n gT s Transmit operationLast byte bit pattern Valid data T a e n c o d i n gLast byte bit Pattern table Encoding examplesTransitions Dpll operation Adjustment ranges and output clocks NRZ and Nrzi encoding Biphase-Level encoding CLK Address Received or a buffer close event occurs, such as end Local loopback Enable Hdlc interruptEnable invalid CRC Enable valid CRCRabort Enable receive abort errorValid CRC Receive abort errorHdlc interrupt Invalid CRCHdata L C D a t a R e g i s t e rHdata L C C o n t r o l R e g i s t e r HmodeClock source L C C l o c k D i v i d e r L o w L C C l o c k D i v i d e r H i g h Address 9002911CDivl Divh Clock enableInterface SPI module Four-wire interface RXD, TXD, CLK, CSProgrammable SPI mode 0, 1, 2, or Master mode internal diagnostic loopbackSPI module structure I c o n t r o l l e rCapture edge Drive edge Timing modes Clocking mode diagramsSPI mode SPI CLK Idle I c l o c k i n g m o d e sClock generation samples SPI master mode SPI slave modeI c l o c k g e n e r a t i o n S t e m b o o t o v e r S P I o p e r a t i o nEntry Name Bootmode10 Address widthAvailable Strapping options EEPROM/FLASH headerEntry Name Description Time to completionI C o n t r o l a n d S t a t u s r e g i s t e r s Configuration registers for the SPI module are located atThis is the primary SPI Configuration register Enable master loopback modeDiscard bytes SPI modeSlave enable O c k G e n e r a t i o n r e g i s t e rUse this register to define the data rate of the interface Bits Access Mnemonic Reset DivisorEnable clock generation Register programming stepsD3102 Not used Write this field to D01 I t i m i n g c h a r a c t e r i s t i c s SPI master timing ParametersParm Description Min Max Unit SPI master timing diagram SPI slave timing parameters SPI slave timing diagram SPI timing characteristics Overview Interface timing, data structure, and error handlingY s i c a l I 2 C b u s I2C busSlave Description Addres Bit E x t e r n a l a d d r e s s e sC o m m a n d i n t e r f a c e Command Name DescriptionRegisterDescription R e g i s t e r sM m a n d T r a n s m i t D a t a r e g i s t e r Address 9005A t u s R e c e i v e D a t a r e g i s t e r 2C Dlen port iicdlenProvide new transmit data Irqcd S t e r a d d r e s s r e g i s t e rScmdl McmdlA v e a d d r e s s r e g i s t e r Address 9005 000C Timing parameter for fast-mode RegisterMask the interrupt to the ARM CPU irqdis T e r r u p t codes Master/slave interrupt codesCode Name Master/slave Description I2C master software driver I2C slave high level driver F t w a r e d r i v e rMaster module normal mode, 16- bit O w c h a r t sSlave module normal mode, 16- bit Real Time Clock Module Address 9006 C G e n e r a l C o n t r o l r e g i s t e rTime date, hour, minute, second operation 12/24 clock mode operation2 4 H o u r r e g i s t e r Calendar operationM e r e g i s t e r HRTHRU Address 9006 000C L e n d a r r e g i s t e rM e Alarm r e g i s t e r Alarm E n a b l e r e g i s t e r L e n d a r Alarm r e g i s t e rAddress 9006 001C E n t F l a g s r e g i s t e rHour event Alarm eventMonth event Date eventHour interrupt Alarm interruptMonth interrupt Date interruptT e r r u p t D i s a b l e r e g i s t e r T e r r u p t E n a b l e S t a t u s r e g i s t e r Address 9006 002C N e r a l S t a t u s r e g i s t e rGeneral Status register Structure ADC moduleADC control block C D M a p r o c e d u r eADC configuration registers are located at offset C c o n t r o l a n d s t a t u s r e g i s t e r sC C o n f i g u r a t i o n r e g i s t e r DMA enable Interrupt statusADC channel select C C l o c k C o n f i g u r a t i o n r e g i s t e r C O u t p u t R e g i s t e r s 0Wait Dout Parameter Symbola Rating Unit E c t r i c a l c h a r a c t e r i s t i c sAbsolute maximum ratings Parameter Symbol a Rating Unit CPU / Memory clock PowerRecommended operating conditions E l e c t r i c a l c h a r a c t e r i s t i c s InputsSym Parameter Conditiona Value Unit Sym Parameter Value Unit OuputsSN74LVC1G17DC Manufacturer Part Number DescriptionNC7SP17 74LVC1G17GWM o r y T i m i n g Sdram burst read 16-bit Sdram burst read 16 bit, CAS latency = Sdram burst write 16 bit Sdram burst read 32 bit Sdram burst read 32 bit, CAS latency = Sdram burst write 32-bit Sdram load mode Sdram refresh mode Clock enable timing Parm Description Min Max Unit Static RAM read cycles with 0 wait states Static RAM asynchronous page mode read, Wtpg = Static RAM read cycle with configurable wait states Static RAM sequential write cycles Static RAM write cycle Static write cycle with configurable wait states CPU Slow peripheral acknowledge timingSlow peripheral acknowledge write Slow peripheral acknowledge readEthernet MII timing Ethernet timingI2C timing Standard Mode Fast Mode Parm Description Min Max UnitSPI slave parameters SPI TimingParm Description Min Max Unit Mod Not SPI master parametersTbclk *8 SPI master mode2 and 3 2-byte transfer SPI master mode 0 and 1 2-byte transferSPI slave mode 2 and 3 2-byte transfer SPI slave mode 0 and 1 2-byte transferParm Description Min Typ Unit S e t a n d h a r d w a r e s t r a p p i n g t i m i n gA G t i m i n g Diagram below pertains to clock timing O c k t i m i n gSystem PLL reference clock Timing Clock timing C k a g e PackagingO c e s s o r D i m e n s i o n s C K a G I N G Processor Dimensions V i s i o n C V i s i o n B

Manufacturer

Part Number

Description

NC7SP17

74LVC1G17GW

SN74LVC1G17DC

NL17SZ17DFT2