Digi NS9215 manual A n s m i t p a c k e t p r o c e s s o r

Receive buffer descriptor field definitions

	E T H E R N E T C O M M U N I C A T I O N M O D U L E	. .
	Transmit packet processor..
		.
Field	Description
W	WRAP bit, which, when set, tells the RX_RD logic that this is the last buffer
	descriptor in the ring. In this situation, the next buffer descriptor is found using the
	appropriate Buffer Descriptor Pointer register.
	When the WRAP bit is not set, the next buffer descriptor is found using an offset of
	0x10 from the current buffer descriptor pointer.
I	When set, tells the RX_RD logic to set RXBUFC in the Ethernet Interrupt Status
	register after the frame has been transferred to system memory.
E	ENABLE bit, which, when set, tells the RX_RD logic that this buffer descriptor is
	enabled. When a new frame is received, pools that do not have the ENABLE bit set
	in their next buffer descriptor are skipped when deciding in which pool to put the
	frame.
	The receive processor can use up to four different-sized receive buffers in system
	memory.
	Note:
	To enable a pool that is currently disabled, change the ENABLE bit from 0 to 1 and
	reinitialize the buffer descriptors pointed to by the Buffer Descriptor Pointer
	register:
	1 Set the ERXINIT bit in the Ethernet General Control Register 1.
	7 Wait for RXINIT to be set in the Ethernet General Status register.
	Change the ENABLE bit only while the receive packet processor is idle.
Buffer pointer	32-bit pointer to the start of the buffer in system memory. This pointer must be
	aligned on a 32-bit boundary.
Status	Lower 16 bits of the Ethernet Receive Status register. The status is taken from the
	receive status FIFO and added to the buffer descriptor after the last word of the
	frame is written to system memory.
F	When set, indicates the buffer is full. The RX_RD logic sets this bit after filling a
	buffer. The system software clears this bit, as required, to free the buffer for future
	use. When a new frame is received, pools that have the F bit set in their next buffer
	descriptor are skipped when deciding in which pool to put the frame.
Buffer length	This is a dual use field:
	When the buffer descriptor is read from system memory, buffer length
	indicates the maximum sized frame, in bytes, that can be stored in this buffer
	ring.

When the RX_RD logic writes the descriptor back from the receive status FIFO into system memory at the end of the frame, the buffer length is the actual frame length, in bytes.Only the lower 11 bits of this field are valid, since the maximum legal frame size for Ethernet is 1522 bytes.

T r a n s m i t p a c k e t p r o c e s s o r

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmit frames are transferred from system memory to the transmit packet processor into a 256-byte TX_FIFO. Because various parts of the transmit frame can

www.digiembedded.com 269