Digi NS9215 manual N a m i c m e m o r y c o n t r o l l e r, R a M I n i t i a l i z a t i o n

M E M O R Y C O N T RO L L E R

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Dynamic memory controller. .

D y n a m i c m e m o r y c o n t r o l l e r

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Write protection Each dynamic memory chip select can be configured for write-protection by setting the appropriate bit in the write protect (P) field on the Dynamic Memory Configuration register. If a write access is performed to a write-protected memory bank, a bus error is generated.

Access sequencing and memory width

The data width of each chip select must be configured by programming the appropriate Dynamic Memory Configuration register. When the chip select data bus width is narrower than the transfer initiated from the current bus master, the internal bus transfer takes several external bus transfers to complete. If chip select 4 is configured as 16-bit wide memory, for example, and a 32-bit read is initiated, the AHB bus stalls while the memory controller reads two consecutive words from memory. During these accesses, the memory controller block demultiplexes the two 16-bit words into one 32-bit word and places the result onto the AHB bus.

Word transfers are the widest transfers supported by the memory controller. Any access tried with a size larger than a word generates an error response.

S D R A M I n i t i a l i z a t i o n

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These steps show how to initialize an external SDRAM device:

1Wait 100 ms after powerup and clocks have stabilized.

2Set the SDRAMInit value in the Dynamic Control register to 11 — Issue SDRAM NOP command.

3Wait 200 ms.

4Set the SDRAMInit value in the Dynamic Control register to 10 — Issue SDRAM PALL (precharge all) command. This precharges all banks and places the SDRAM device into the all banks idle state.

5Force frequent refresh cycles by writing a 1 to the Dynamic Refresh register. This provides a memory refresh every 16 memory clock cycles.

6Wait until eight SDRAM refresh cycles have occurred (128 memory clock cycles).

7Program the appropriate operational value to the Dynamic Refresh register.

8Program the appropriate operational value to the Dynamic Ras and Cas N regis- ter.

9Program the appropriate operational value to the Dynamic Configuration N regis- ter, with the exception of the buffer enable bit, which must be set to 0 during initialization.

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