Digi NS9215 manual Split transfers Arbiter configuration example

S Y S T E M C O N T RO L M O D U L E

System bus arbiter

SPLIT transfers

Arbiter configuration example

If the bus is granted to a default master and continues to be in the IDLE state longer than a specified period of time, an AHB bus arbiter timeout is generated. An AHB bus arbiter timeout can be configured to interrupt the CPU or to reset the chip.

A SPLIT transfer occurs when a slave is not ready to perform the transfer. The slave splits, or masks, its master, taking away the master’s bus ownership and allowing other masters to perform transactions until the slave has the appropriate resources to perform its master’s transaction.

The bus arbiter supports SPLIT transfers. When a SPLIT response is issued by a slave, the current master is masked for further bus requesting until a corresponding hsplit_x[15:0] signal is issued by the slave indicating that the slave is ready to complete the transfer. The arbiter uses the hsplit_x[15:0] signals to unmask the corresponding master, and treats the master as the highest-priority requester for the immediate next round of arbitration. The master eventually is granted access to the bus to try the transfer again.

Note: The arbiter automatically blocks bus requests with addresses directed at a “SPLITting” slave until that SPLIT transaction is completed.

This example shows how to configure the AHB arbiter to guarantee bandwidth to a given master. These are the conditions in this example:

5 AHB masters — CPU, Ethernet Rx, Ethernet Tx, IO hub, and external DMA AHB clock frequency — 75 MHz

Average access time per 16-byte memory access — 4 clock cycles The ARM926EJ-S is guaranteed one-half the total memory bandwidth

In this example, the bandwidth for each master can be calculated using this formula:

Bandwidth per master:

=[(75MHz/2) / (4 clock cycles per access x 5 masters)] x 16 bytes

=60MB/master

Note: The worst case scenario is that there are 90 Mbps total to be split by all 5 masters.

if this meets the requirements of all the masters, the AHB arbiter is programmed like this:

BRC0[31:24]	= 8’b1_0_00_0000	channel enabled, 100%, ARM7EJ-S
BRC0[23:16]	= 8’b1_0_00_0001	channel enabled, 100%, Ethernet Rx
BRC0[15:8]	= 8’b1_0_00_0000	channel enabled, 100%, Ethernet TX
BRC0[7:0]	= 8’b1_0_00_0101	channel enabled, 100%, IO hub
BRC1[31:24]	= 8’b1_0_00_0011	channel enabled, 100%, Ext DMA

140Hardware Reference NS9215