Digi NS9215 manual Rxdoneb, Rxdonec, Rxdoned, Rxnobuf, Rxbufful, Stovfl, Txbufc, Txbufnr, Txdone

E T H E R N E T C O M M U N I C A T I O N M O D U L E

Ethernet Interrupt Status register

Bits	Access	Mnemonic	Reset	Description
D21	R/C	RXDONEB	0	Assigned to RX interrupt.
				Complete receive frame stored in pool B of system
				memory.
D20	R/C	RXDONEC	0	Assigned to RX interrupt.
				Complete receive frame stored in pool C of system
				memory.
D19	R/C	RXDONED	0	Assigned to RX interrupt.
				Complete receive frame stored in pool D of system
				memory.
D18	R/C	RXNOBUF	0	Assigned to RX interrupt.
				No buffer is available for this frame due to one of
				these conditions:
				All four buffer rings being disabled
				All four buffer rings being full
				No available buffer big enough for the frame
D17	R/C	RXBUFFUL	0	Assigned to RX interrupt.
				No buffer is available for this frame because all four
				buffer rings are disabled or full.
D16	R/C	RXBR	0	Assigned to RX interrupt.
				New frame available in the RX_FIFO. This bit is
				used for diagnostics.
D15:07	N/A	Reserved	N/A	N/A
D06	R/C	STOVFL	0	Assigned to TX interrupt.
				Statistics counter overflow. Individual counters can
				be masked using the Carry Register 1 and 2 Mask
				registers. The source of this interrupt is cleared by
				clearing the counter that overflowed, and by clearing
				the associated carry bit in either Carry Register 1 or
				Carry Register 2 by writing a 1 to the bit.
D05	R	Not used	0	Always write as 0.
D04	R/C	TXBUFC	0	Assigned to TX interrupt.
				I bit set in the Transmit Buffer Descriptor and buffer
				closed.
D03	R/C	TXBUFNR	0	Assigned to TX interrupt.
				F bit not set in the Transmit Buffer Descriptor when
				read from the TX Buffer descriptor RAM.
D02	R/C	TXDONE	0	Assigned to TX interrupt.
				Frame transmission complete.

318Hardware Reference NS9215