Digi NS9215 manual Access permissions and domains Translated entries

WO R K I N G W I T H T H E C P U

MemoryManagement Unit (MMU)

Access permissions and domains

Translated entries

Invalidate entire TLB using R8: TLB Operations register (see “R8:TLB Operations register” on page 97).

Invalidate TLB entry selected by MVA, using R8: TLB Operations register (see “R8:TLB Operations register” on page 97).

Lockdown of TLB entries using R10: TLB Lockdown register (see “R10:TLB Lockdown register” on page 101).

For large and small pages, access permissions are defined for each subpage (1 KB for small pages, 16 KB for large pages). Sections and tiny pages have a single set of access permissions.

All regions of memory have an associated domain. A domain is the primary access control mechanism for a region of memory. It defines the conditions necessary for an access to proceed. The domain determines whether:

Access permissions are used to qualify the access. The access is unconditionally allowed to proceed. The access is unconditionally aborted.

In the latter two cases, the access permission attributes are ignored.

There are 16 domains, which are configured using R3: Domain Access Control register (see “R3:Domain Access Control register” on page 91).

The TLB caches translated entries. During CPU memory accesses, the TLB provides the protection information to the access control logic.

When the TLB contains a translated entry for the modified virtual address (MVA), the access control logic determines whether:

Access is permitted and an off-chip access is required — the MMU outputs the appropriate physical address corresponding to the MVA.

Access is permitted and an off-chip access is not required — the cache services the access.

Access is not permitted — the MMU signals the CPU core to abort.

If the TLB misses (it does not contain an entry for the MVA), the translation table walk hardware is invoked to retrieve the translation information from a translation table in physical memory. When retrieved, the translation information is written into the TLB, possible overwriting an existing value.

At reset, the MMU is turned off, no address mapping occurs, and all regions are marked as noncachable and nonbufferable.

106Hardware Reference NS9215