Digi NS9215 manual Deprecated Chip sleep enable, New designs should not use this bit

S Y S T E M C O N T RO L M O D U L E

Power Management

Register bit

assignment	Bits	Access	Mnemonic	Reset	Description
	D31	R/W	Slp en	0x0	Deprecated Chip sleep enable
					This control bit is provided for backwards
					compatibility with software written for the NS9750
					and NS9360 processors, and should not be used by
					new software.
					System software writes a 1 to this bit to stop the
					clock to the CPU. Note that software is responsible
					for stopping the clocks to all other modules except
					the wakeup module(s) before setting this bit. When
					this bit is set, the clock to the CPU is stopped and the
					CPU is held in reset.
					New designs should not use this bit.
					They should stop the clock by executing the
					following coprocessor instruction:
					MCR p15, 0<Rd>, c7, c0, 4
					This instruction places the ARM9 CPU into wait for
					interrupt mode. In wait for interrupt mode, the clock
					is stopped to the CPU but reset is not asserted.
					The CPU resumes and executes a CPU Wake
					Interrupt when activity is detected by one of the
					wakeup modules selected by the other bits in this
					register. The PC will be restored to the address after
					the coprocessor instruction that stopped the CPU’s
					clock when the CPU Wake Interrupt ISR completes.
					The processor can not wake up on a timer interrupt
					because the system timers are stopped when the
					processor enters wake for interrupt mode.
	D30	R/W	HW clk scale	0x0	Hardware clock scale control
					0 Disable hardware clock scale control
					1 Enable hardware clock scale control
					Used by hardware to increase the clock rate when
					activity is found on one of the modules enabled as a
					wakeup module.
					Hardware automatically increases the system clock
					frequencies to the value set by the max clock scale
					control bit in the Clock Control register.
	D29:22	N/A	Reserved	N/A	N/A
	D21	R/W	MemSRFEn	0x0	SDRAM self refresh control
					0 Memory self refresh control disabled
					1 Memory self refresh control enabled

When enabled, the memory controller is automatically placed in self refresh mode when the CPU is in sleep mode and taken out of self refresh upon wakeup.

188Hardware Reference NS9215