I / O C O N T RO L M O D U L E

Memory Bus Configuration register

Bit(s)

Access

Mnemonic

Reset

Description

 

 

 

 

 

D14:12

R/W

CS4

0x6

Controls which system memory chip select is

 

 

 

 

routed to CS4

 

 

 

 

000

dy_cs_0

 

 

 

 

001

dy_cs_1

 

 

 

 

010

dy_cs_2

 

 

 

 

011

dy_cs_3

 

 

 

 

100

st_cs_0

 

 

 

 

101

st_cs_1

 

 

 

 

110

st_cs_2 (default)

 

 

 

 

111

st_cs_3

 

 

 

 

 

D17:15

R/W

CS5

0x2

Controls which system memory chip select is

 

 

 

 

routed to CS5

 

 

 

 

000

dy_cs_0

 

 

 

 

001

dy_cs_1

 

 

 

 

010

dy_cs_2 (default)

 

 

 

 

011

dy_cs_3

 

 

 

 

100

st_cs_0

 

 

 

 

101

st_cs_1

 

 

 

 

110

st_cs_2

 

 

 

 

111

st_cs_3

 

 

 

 

 

D20:18

R/W

CS6

0x7

Controls which system memory chip select is

 

 

 

 

routed to CS6

 

 

 

 

000

dy_cs_0

 

 

 

 

001

dy_cs_1

 

 

 

 

010

dy_cs_2

 

 

 

 

011

dy_cs_3

 

 

 

 

100

st_cs_0

 

 

 

 

101

st_cs_1

 

 

 

 

110

st_cs_2

 

 

 

 

111

st_cs_3 (default)

 

 

 

 

 

D23:21

R/W

CS7

0x3

Controls which system memory chip select is

 

 

 

 

routed to CS7

 

 

 

 

000

dy_cs_0

 

 

 

 

001

dy_cs_1

 

 

 

 

010

dy_cs_2

 

 

 

 

011

dy_cs_3 (default)

 

 

 

 

100

st_cs_0

 

 

 

 

101

st_cs_1

 

 

 

 

110

st_cs_2

 

 

 

 

111

st_cs_3

 

 

 

 

 

D24

R/W

DHPUDIS

0x0

High data bus pullup control

 

 

 

 

0 Enable pullup resistors on data[31:16]

 

 

 

 

1 Disable pullup resistors on data[31:16]

 

 

 

 

Note:

Bits 15:00 are output and controlled

 

 

 

 

 

through GPIO

78Hardware Reference NS9215

Page 78
Image 78
Digi NS9215 manual High data bus pullup control

NS9215 specifications

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