Digi NS9215 manual R i p h e r a l D M a w r i t e a c c e s s, Peripheral DMA single read access

Peripheral DMA single read access

CLK

st_cs_n[n]

st_oe_n

ADDR

PDEN

DQ

E X T E R N A L D M A	. .
Peripheral DMA write access..
	.

Address Valid

DATA VALID

Peripheral DMA burst read access

CLK

st_cs_n[n]

st_oe_n
ADDR	ADDR0	ADDR1
PDEN
DQ	DATA0	DATA1

P e r i p h e r a l D M A w r i t e a c c e s s

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The diagrams in this section describe how the DMA engine performs write accesses of an external peripheral. The CLK signal shown is for reference, and its frequency is equal to the speed grade of the part. For peripheral writes, the PDEN signal is an AND function of the active status of st_cs_n[n] and we_n. Write data into the peripheral on the falling edge of the PDEN signal. Data and control signals are always held after the falling edge of PDEN for one reference CLK cycle.

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