Digi NS9215 Transmit buffer descriptor format, Transmit buffer Descriptor field, Definitions

E T H E R N E T C O M M U N I C A T I O N M O D U L E

Transmit packet processor

Transmit buffer descriptor format

reside in different buffers in system memory, several buffer descriptors can be used to transfer the frame.

All buffer descriptors (that is, up to 64) are found in a local TX buffer descriptor RAM. This is the transmit buffer descriptor format.

	31	30	29	28		16	15		0
OFFSET + 0					Source Address
OFFSET + 4					Buffer Length (11-bits used)
OFFSET + 8
					Destination Address (not used)
OFFSET + C
	W	I	L	F	Reserved			Status

Transmit buffer

descriptor field	Field	Description
definitions
	W	WRAP bit, which, when set, tells the TX_WR logic that this is the last buffer descriptor
		within the continuous list of descriptors in the TX buffer descriptor RAM. The next
		buffer descriptor is found using the initial buffer descriptor pointer in the TX Buffer
		Descriptor Pointer register (TXPTR).
		When the WRAP bit is not set, the next buffer descriptor is located at the next entry
		in the TX buffer descriptor RAM.
	I	When set, tells the TX_WR logic to set TXBUFC in the Ethernet Interrupt Status
		register when the buffer is closed due to a normal channel completion.
	Buffer pointer	32-bit pointer to the start of the buffer in system memory. This pointer can be aligned
		on any byte of a 32-bit word.
	Status	Lower 16 bits of the Ethernet Transmit Status register. The status is returned from
		the Ethernet MAC at the end of the frame and written into the last buffer descriptor
		of the frame.
	L	When set, tells the TX_WR logic that this buffer descriptor is the last descriptor that
		completes an entire frame. This bit allows multiple descriptors to be chained together
		to make up a frame.

270Hardware Reference NS9215