Digi NS9215 manual Wtpg, Asynchronous page mode read after the first wait state

M E M O R Y C O N T RO L L E R

. . .

Static Memory Write Delay 0–3 registers. .

modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low-power or disabled mode.

Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							Reserved
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					Reserved								WTPG

Register bit

assignment	Bits	Access	Mnemonic	Description
	D31:05	N/A	Reserved	N/A (do not modify)
	D04:00	R/W	WTPG	Asynchronous page mode read after the first wait state
				(WAITPAGE)
				00000–11110	(n+1) clk_out cycle for read access time. For

asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE+1) x tclk_out

11111 32 clk_out cycles read access time (reset value on reset_n) Number of wait states for asynchronous page mode read accesses after the first read.

S t a t i c M e m o r y W r i t e D e l a y 0 – 3 r e g i s t e r s

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Address: A070 0214 / 0234 / 0254 / 0274

The Static Memory Write Delay 0–3 registers allow you to program the delay from the chip select to the write access. These registers control the overall period for the write cycle. It is recommended that these registers be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low-power or disabled mode.These registers are not used if the extended wait bit is enabled in the related Static Memory Configuration register.

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