Digi NS9215 manual L C D a t a R e g i s t e r, Hdata

				S E R I A L C O N T RO L M O D U L E : H D L C	. .
				HDLC Data Register 1..
					.
Bits	Access	Mnemonic	Reset	Description
				Transmit idle
D01	R/W1TC	TX_IDLE	0
				Indicates that the transmitter has moved from the active
				state to the idle state. The transmitter moves from the active
				state to the idle state when the transmit FIFO is empty and
				the transmitter is not actively shifting out data.
D00	R/W1TC	RX_IDLE	0	Receive idle
				Indicates that the receiver has moved from the active state
				to the idle state. The receiver moves from the active state to
				the idle state when a start bit has not been received after the
				previous stop bit.

H D L C D a t a R e g i s t e r 1

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Address: 9002_9100

HDLC Data Register 1 reads data from the receive buffer and load data in the transmit buffer. This register is for debug purposes only.

Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						Reserved
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			Reserved									HDATA

Register bit

assignment	Bits	Access	Mnemonic	Reset	Description
	D31:08	N/A	Reserved	0	N/A
	D07:00	R/W	HDATA	0	Read	Returns the contents of the receive buffer
					Write	Loads the transmit buffer with a byte of data

H D L C D a t a R e g i s t e r 2

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Address: 9002_9104

HDLC Data Register 2 writes the last byte of data of a frame after which the CRC and closing flag are transmitted. This register is for debug purposes only.

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