Digi NS9215 manual M e r M a s t e r C o n t r o l r e g i s t e r, Eic, AHB Error Interrupt Clear

S Y S T E M C O N T RO L M O D U L E

Timer Master Control register

Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			Reserved					EIC				Reserved
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					Reserved						SERDC			Reserved

Register bit

assignment	Bits	Access	Mnemonic	Reset	Description
	D31:24	N/A	Reserved	N/A	N/A
	D23	R/W	EIC	0x0	AHB Error Interrupt Clear
					Write a 1, then a 0 to this register to clear the AHB
					error interrupt and to clear the AHB Error Detect
					Status 1 and AHB Error Detect Status 2 registers.
	D22:05	N/A	Reserved	N/A	N/A
	D04	R/W	SERDC	0x0	AHB Slave Error Response Detect Config
					0	Record error only
					1	Generate IRQ
	D03:00	N/A	Reserved	N/A	N/A

T i m e r M a s t e r C o n t r o l r e g i s t e r

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Address: A090 0024

The Timer Master Control register resets and enables the timer in groups, which is useful when using the timers in PW applications.

Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			Reserved							T9RSE	T9LSE	T9HSE	T8RSE	T8LSE	T8HSE
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
T7RSE	T7LSE	T7HSE	T6RSE	T6LSE	T6HSE	T9E	T8E	T7E	T6E	T5E	T4E	T3E	T2E	T1E	T0E

162Hardware Reference NS9215