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Digi NS9215 manual M e r 6 9 H i g h a n d L o w S t e p r e g i s t e r s, High step direction

Models: NS9215

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S Y S T E M C O N T RO L M O D U L E

Timer 6–9 High and Low Step registers

T i m e r 6 – 9 H i g h a n d L o w S t e p r e g i s t e r s

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Addresses: A090 0098 / 009C / 00A0 / 00A4

The Timer 6–9 High and Low Step registers contain the high and low step registers for the enhanced PWM features available in timers 6 through 9.

Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

Hi
Step							Hi Step
Dir

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Lo							Lo Step
Step							Lo Step
Dir

Register bit

assignment	Bits	Access	Mnemonic	Reset	Description

	D31	R/W	Hi Step Dir	0x0	High step direction
					0	Subtract the high step value from the original
						high register value to increase the high time.
					1	Add the high step value to the original high
						register value to decrease the high time.

	D30:16	R/W	Hi Step	0x0	High step
					This value is either added or subtracted from the
					original high register value once each cycle.

	D15	R/W	Lo Step Dir	0x0	Low step direction
					0	Subtract the low step value from the original low
						register value to increase low time 2.
					1	Add the low step value to the original low
						register value to decrease low time 2.

	D14:00	R/W	Lo Step	0x0	Low step
					This value is either added or subtracted from the
					original low register value once each cycle.

T i m e r 6 – 9 R e l o a d S t e p r e g i s t e r s

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Addresses: A090 00A8 / 00AC / 00B0 / 00B4

The Timer 6–9 reload Step registers contain the reload step registers for the enhanced PWM features available in timers 6 through 9.

172Hardware Reference NS9215

Image 172

Digi NS9215 manual M e r 6 9 H i g h a n d L o w S t e p r e g i s t e r s, M e r 6 9 R e l o a d S t e p r e g i s t e r s

Contents

NS9215 Hardware Reference 90000847C Release date 10 AprilPage Page Page Contents A p t e r 3 W o r k i n g w i t h t h e C P U 102 105 A p t e r 4 S y s t e m C o n t r o l M o d u l e 137 141 A p t e r 5 M e m o r y C o n t r o l l e r 203 Sram Bit wide configuration 228 229 Hardware Reference NS9215 HT1 315 A p t e r 7 E x t e r n a l D M a 339 Hardware Reference NS9215 A p t e r 9 I / O H u b M o d u l e 363 Hardware Reference NS9215 A p t e r 1 1 S e r i a l C o n t r o l D u l e H D L C 415 Hardware Reference NS9215 A p t e r 1 4 R e a l T i m e C l o c k M o d u l e 459 A p t e r 1 6 T i m i n g 479 A p t e r 1 7 P a c k a g i n g 513 Hardware Reference NS9215 Pinout Heading DescriptionPin Signal Description M o r y b u s i n t e r f a c eN O U T 2 6 Pin Signal H e r n e t i n t e r f a c e M a CSdram RAS Sdram CASN e r a l p u r p o s e I / O G P I O DCD Uart a CTS Uart aDSR Uart a RXD Uart aDCD / TXC Uart C CTS Uart CI2C SCL PicdbgdatainiDCD Uart B CTS Uart BDSR Uart B RXD Uart BDSR Uart D RXD Uart DRI Uart D TXC / DTR Uart DPin Signal Description PIC1CLKI PIC1CLKOPin Signal Description PIC0CLKI PIC0CLKOPin Signal Description Pin Signal Description Pin Signal Description S t e m c l o c k I/O ODSystem clock drawing RTC clock and battery backup drawing S t e m m o d eSysmode2 Sysmode1 Sysmode0 Description S t e m r e s e t SPI YESA G T e s t Adcvss R a n d b a t t e r y b a c k e d l o g i c POR VSSW e r a n d g r o u n d GNDPower and ground Address Description Access Reset value N t r o l a n d S t a t u s r e g i s t e r sSystem memory bus I/O control Register address MapControl and Status registers I O C o n f i g u r a t i o n r e g i s t e r s Gpio configuration optionsBits Mnemonic Description Configuration Register #0 Configuration Register #1Bits Access Mnemonic Reset Description Address A0902000Configuration Register #2 Configuration Register #3Address A0902008 Address A090200CConfiguration Register #4 Configuration Register #5Address A0902010 Address A0902014Configuration Register #6 Configuration Register #7Address A0902018 Address A090201CConfiguration Register #8 Configuration Register #9Address A0902020 Address A0902024Configuration Register #10 Configuration Register #11Address A0902028 Address A090202CConfiguration Register #12 Configuration Register #13Address A0902030 Address A0902034Configuration Register #14 Configuration Register #15Address A0902038 Address A090203CConfiguration Register #16 Configuration Register #17Address A0902040 Address A0902044Configuration Register #18 Configuration Register #19Address A0902048 Address A090204CConfiguration Register #20 Configuration Register #21Address A0902050 Address A0902054Configuration Register #22 Configuration Register #23Address A0902058 Address A090205CConfiguration Register #24 Configuration Register #25Address A0902060 GPIOAddress A0902064Configuration Register #26 Address A0902068Gpio Control I O C o n t r o l r e g i s t e r sAddress A090206C Address A0902070 Address A0902074 Address A0902078 Gpio Status I O S t a t u s r e g i s t e r sAddress A0902080 Address A0902084 Address A0902088 M o r y B u s C o n f i g u r a t i o n r e g i s t e rAddress A090208C CS0 CS1CS2 CS3High data bus pullup control Apudis Memory Bus Configuration register Working with the CPU About the processorProcess block Diagram S t r u c t i o n s e t sArm926EJ-S ARM instruction set Thumb instruction setJava instruction set Accessing CP15 registersARM926EJ-S system addresses Address manipulation example Terms and abbreviations Mnemonics for these instructions areTerm Abbreviation Description For readsBe ZERO, does not cause any physical damage to the chip Register summaryRegister Reads Writes TLBThis is the contents of the ID code register Writing to register R0 is UnpredictableR0 ID code Any value other than 1 or 2. Note this exampleCache type register and field description Dsize and Isize fieldsField contains these bits Field DescriptionO n t r o l r e g i s t e r Size field Cache sizeAssoc field Associativity Len field Cache line lengthBit functionality Control registerBits Name Function ICache DCache behaviorCache BehaviorCRm and opcode2 fields should be Zero when writing to R2 Access permissions and instructionsR a n s l a t i o n T a b l e B a s e r e g i s t e r O m a i n a c c e s s C o n t r o l r e g i s t e rFault S t a t u s r e g i s t e r s Access instructionsE g i s t e r Register bitsStatus and domain fields Fault a d d r e s s r e g i s t e rPriority Source Size Status Domain A c h e O p e r a t i o n s r e g i s t e r Function DescriptionFunction/operation Data format Instruction Cache operation functionsMVA Set/Way example Test and clean DCache instructions Modified virtual address format MVA Set/Way formatTest, clean, and invalidate DCache instruction L B O p e r a t i o n s r e g i s t e rUnpredictable Operation Data InstructionA c h e L o c k d o w n r e g i s t e r Modified virtual address format MVACache ways That allows you to control each cache way independentlyAccess Instruction or data lockdown registerInstructions Modifying the Cache Lockdown register Register formatFor each of the cache lines to be locked down in cache way Cache unlock procedure 0 T L B L o c k d o w n r e g i s t e rBit Which region the TLB entry is placed1 a n d R 1 2 r e g i s t e r s 3 P r o c e s s I D r e g i s t e rProgramming instructions Sample code sequence Use these instructions to program the TLB Lockdown registerFcse PID register Access instructions Performing a fast context switchRegister format This is the format of the Fcse PID register Function Data ARM instructionContext ID register Access instructions Accessing reading or writing this register is reserved4 r e g i s t e r 5 T e s t a n d d e b u g r e g i s t e rMMU Features M o r y M a n a g e m e n t U n i t M M UState space servo control Protection schemeAccess permissions and domains Translated entries MMU program accessible registers Address translation Register Bits DescriptionTranslation table base TTB register FormatTable walk process First-level fetchFirst-level descriptor First-level fetch concatenation and addressTable descriptors Bits Section Coarse Fine Description Section descriptor FormatValue Meaning Description Section descriptor Bit description Fine page tableDescriptor Bits Description113 Second-level descriptor Second-level descriptor format Second-level descriptor pagesSecond-level descriptor least significant bits Second-level descriptor bit assignmentsBits Large Small Tiny Description Translation sequence for large page references Translating sequence for small page references Translation Sequence for tiny ReferencesLevel descriptor More informationU Fault s a n d C P U a b o r t s Priority encoding table Fault Address register FAR Domain Fault Address registerFAR values for Multi-word TransfersCompatibility issues Specifying access permissionsInterpreting access permission bits M a i n a c c e s s c o n t r o lFault c h e c k i n g s e q u e n c e Privileged permissions User permissionsNo access 00 Reserved Check domain status Fault checking sequence A b l i n g a n d d i s a b l i n g t h e M M U T e r n a l a b o r t sEnabling B s t r u c t u r e DisablingCache features C h e s a n d w r i t e b u f f e rWrite buffer Enabling the caches Bit settings SettingsR1 register C and M bits for DCache DCacheC h e M V a a n d S e t / W a y f o r m a t s Description ARM926EJ-S behavior Table C Table B BitGeneric, virtually indexed, virtually addressed cache ARM926EJ-S Cache formatN c a c h a b l e i n s t r u c t i o n f e t c h e s This figureFor example, with a 4-way cache a = Self-modifying codeAHB behavior Instruction Memory Barrier Sample IMB sequences Noncachable instruction fetches Features S i n t e r c o n n e c t i o nS t e m b u s a r b i t e r Ownership Until the transaction completesMaster will not occupy the system bus Locked bus sequence Relinquishing the busSplit transfers Arbiter configuration example D r e s s d e c o d i n g Address range Size System functionsO g r a m m a b l e t i m e r s Software watchdog timerMaster Name Hmaster30 assignment N e r a l p u r p o s e t i m e r s / c o u n t e r s Gptc characteristics Control fieldSource clock frequency Bit mode options S i c P W M f u n c t i o nA d r a t u r e d e code r f u n c t i o n H a n c e d P W M f u n c t i o nSample enhanced PWM waveform Input signals NC No change CW Clockwise CCW Counter clockwise Err ErrorQuadrature Encoding truth CCWTesting signals Timer supportMonitors how far the encoder has moved Typical application Digital filterT e r r u p t c o n t r o l l e r FIQ interruptsIRQ interrupts VectorIRQ characteristics Interrupt sources IRQ FIQInterrupt sources are assigned as shown Interrupt ID Interrupt sourceN f i g u r a b l e s y s t e m a t t r i b u t e s L c o n f i g u r a t i o nConfiguring the powerup settings PLL configuration and control system block diagramO t s t r a p i n i t i a l i z a t i o n Pin name Configuration bits S t e m c o n f i g u r a t i o n r e g i s t e r s Offset 3124 2316 158155 Isaddr System Memory Chip Select 0 Dynamic Memory Mask N e r a l a r b i t e r C o n t r o l r e g i s t e r C 0 , B R C 1 , B R C 2 , a n d B R C 3 r e g i s t e r sAddress A090 RegisterB Error D e t e c t S t a t u s Channel enable bitChannel allocation Register Register bit assignment This is how the channels are assigned in the four registersAddress A090 001C EDS1Not reset CPU instruction error Not reset CPU data errorNot reset AHB error response Transaction type write or readAHB Error Interrupt Clear AHB Slave Error Response Detect ConfigM e r M a s t e r C o n t r o l r e g i s t e r EICTimer 9 reload step enable Timer 9 low step enableTimer 9 high step enable Timer 8 reload step enableM e r 0 4 C o n t r o l r e g i s t e r s Addresses A090 0190 / 0194 / 0198 / 019C / 01A0Timer enable Capture and compare mode functionsDebug mode Timer clock selectM e r 5 C o n t r o l r e g i s t e r Address A090 01A4Reload mode TM2M e r 6 9 C o n t r o l r e g i s t e r s Addresses A090 01A8 / 01AC / 01B0 / 01B4D3118 Reserved D1716 M e r 6 9 H i g h r e g i s t e r s M e r 6 9 L o w r e g i s t e r s M e r 6 9 H i g h a n d L o w S t e p r e g i s t e r s M e r 6 9 R e l o a d S t e p r e g i s t e r sHigh step direction High stepReload step direction Reload stepM e r 0 9 R e a d a n d C a p t u r e r e g i s t e r Interrupt Vector Address register Individual register mappingRegister 3124 2316 1508 0700 Interrupt enable A D D R r e g i s t e rInvert Interrupt typeInterrupt service routine address T e r r u p t S t a t u s a c t i v eInterrupt status active ISAT e r r u p t S t a t u s R a w F t w a r e W a t c h d o g C o n f i g u r a t i o nAddress A090 016C IsrawSoftware watchdog enable Software watchdog timer clock selectF t w a r e W a t c h d o g T i m e r Software watchdog interrupt clearO c k C o n f i g u r a t i o n r e g i s t e r Watchdog timerAddress A090 017C Clock scale control Max clock scale controlCPU clock select Memory clock outIO hub D u l e R e s e t r e g i s t e rEthernet MAC Module Reset register resets each module on the AHB bus Reset statusRST Stat I2CMiscellaneous System Configuration and Status register Boot mode Endian modeMisaligned bus address response mode Internal register access mode bitPLL frequency formula Register Register bit assignment L C o n f i g u r a t i o n r e g i s t e rPLL bypass W e r M a n a g e m e n t Address A090 018CIntid Interrupt IDDeprecated Chip sleep enable New designs should not use this bitHardware clock scale control Sdram self refresh controlCPU wake interrupt clear RTC wakeupI2C wakeup SPI wakeupAddress A090 022C B B u s a c t i v i t y S t a t u sAddresses A090 01D0 / 01D4 Chip select 0 disable RegistersAddresses A090 01D8 / 01DC Chip select 0 baseAddresses A090 01E0 / 01E4 Chip select 1disableChip select 1 base Addresses A090 01E8 / 01EC Chip select 2 disableChip select 2 base Addresses A090 01F0 / 01F4 Chip select 3 disableChip select 3 base Addresses A09001F8 / 01FC Chip select 0 maskChip select 1 disable Addresses A090 0200Addresses A090 0208 / 020C N I D r e g i s t e r Genid STSStatus CLRRTC standby mode status C M o d u l e C o n t r o l r e g i s t e rRTC Module Control register controls the RTC module PolarityRTC standby mode RTC clock ready interrupt statusRTC module interrupt status RTC clock ready interrupt clearRTC Module Control register Memory controller provides these features With and without asynchronous page modeStatic memory features, such as Amba 32-bit AHB compliancyW p o w e r o p e r a t i o n Power-on reset memory map M o r y m a pExample Boot from flash Sdram remapped after boot Device Write protect Mode Buffer A t i c m e m o r y c o n t r o l l e rROM SramWrite protection Extended wait transfers Be awareA t i c m e m o r y i n i t i a l i z a t i o n Access sequencing and memory width Wait state generationMemory mapped peripherals Programmable enable Output enable programmable delayA t i c m e m o r y r e a d c o n t r o l ROM, SRAM, and FlashExternal memory read transfer with zero wait states External memory read transfer with two wait statesTiming parameter Value WAITRD2 WAITOEN0 WAITPAGEN/A WAITWRN/AExternal memory read transfers with zero wait states WAITENN/A WAITTURNN/ABurst of zero wait states with fixed length Burst of two wait states with fixed lengthExternal memory page mode read transfer Y n c h r o n o u s p a g e m o d e r e a dExternal memory 32-bit burst read from 8-bit memory WAITRD2 WAITOEN0 WAITPAGE1 WAITWRN/A WAITWENN/A WAITTURNN/ATiming parameters Value WAITRD0 WAITOEN0 WAITPAGE0 WAITWRN/A WAITWENN/A WAITTURNN/AWrite enable programming delay A t i c m e m o r y w r i t e c o n t r o lWait states added between external read and write transfers External memory write transfer with zero wait statesExternal memory write transfer with two wait states WAITRDN/A WAITOENN/A WAITPAGEN/A WAITWR0 WAITWEN0 WAITTURN0 S t u r n a r o u n d S t u r n a r o u n d T i m i n g a n d p a r a m e t e r sRead followed by write with no turnaround WAITRD0 WAITOEN0 WAITPAGEN/A WAITWR0 WAITWEN0 WAITTURN0Write followed by a read with no turnaround Read followed by a write with two turnaround cyclesT e l a n e c o n t r o l WAITRD0 WAITOEN0 WAITPAGEN/A WAITWR0 WAITWEN0 WAITTURN2D r e s s c o n n e c t i v i t y Memory banks constructed from 16-or 32-bit memory devices Memory banks constructed from 16-bit memory2Mx32 ROM N a m i c m e m o r y c o n t r o l l e r Access sequencing and memory widthR a M I n i t i a l i z a t i o n Left-shift value -bit wide data bus Sdram RBC Device size Configuration Load Mode register left shiftBit Parameter Parameter description 256M 8M x 16M x 32M x 512M 64M x Bit wide Configuration Signal 16M device 64M device 128M 256M 512MDevice Signal Left-shift value -bit wide data bus Sdram BRCBA0 BA1G i s t e r s Register mapOnly. Bursting is not allowed Address Register DescriptionTRWL, tRDL N t r o l r e g i s t e r Reset valuesAddress A070 Bits Access Mnemonic Description Low-power modeMemory controller enable Address mirrorA t u s r e g i s t e r N f i g u r a t i o n r e g i s t e rSelf-refresh acknowledge Srefack Write buffer statusN a m i c M e m o r y C o n t r o l r e g i s t e r ENDSync/Flash reset/power down signal dypwrn Dynamic memory clock enableSdram initialization Self-refresh request SrefreqRefresh timer RefreshRead data strategy Active to precharge command period tRAS Precharge command period tRPRAS Srex Address A070 003CSelf-refresh exit time tSREX Last-data-out to active command time tAPR APRData-in to active command tDAL or tAPW DALActive to active command period tRC Address A070 004CRFC Auto-refresh period and auto-refresh to active commandPeriod Exit self-refresh to active time command XSRLoad mode register to Active Command Time RRDActive Bank a to Active Bank B MRDExternal wait timeout A t i c M e m o r y E x t e n d e d W a i t r e g i s t e rExample Address A070 0100 / 0120 / 0140Write protect BdmcAddress mapping AM1Memory Configuration Address mappingFor the Dynamic 119 DescriptionAddress A070 0104 / 0124 / 0144 For a chip select connected to Select this mappingRAS latency active to read/write delay CASCAS latency Do not modifyBuffer enable PsmcBsmc Extended waitChip select polarity Byte lane stateMode Bmode Burst modeMemory width Wait write enable Waitwen Wait output enable WaitoenAddress A070 0208 / 0228 / 0248 WwenNonpage mode read wait states or asynchronous page mode Read first access wait state WaitrdA t i c M e m o r y R e a d D e l a y 0 3 r e g i s t e r s WtrdAsynchronous page mode read after the first wait state WtpgWtwr Address A070 0218 / 0238 / 0258Write wait states Waitwr Wttn Bus turnaround cycles WaitturnStaticMemory Turn Round Delay 0-3 registers Features Common acronyms Ethernet Communication ModuleH e r n e t M a C Ethernet communications moduleMAC module block diagram Features Feature DescriptionA t i o n a d d r e s s l o g i c S a L PHY interface mappingsStation address logic Media Independent InterfaceA t i s t i c s m o d u l e MAC receiverEthernet front- end module EFE H e r n e t f r o n t e n d m o d u l eReceive packet processor C e i v e p a c k e t p r o c e s s o r Transmit packet processorReceive buffer descriptor format Transferring a frame to system memoryReceive buffer descriptor format description A n s m i t p a c k e t p r o c e s s o r Receive buffer descriptor field definitionsTransmit buffer Descriptor field Transmit buffer descriptor formatDefinitions Transmitting a frame Frame TransmittedSuccessfully UnsuccessfullyT e r r u p t s H e r n e t s l a v e i n t e r f a c eInterrupt condition Description S e t s Bit field Register Active Default Modules reset StateStatus bits L t i c a s t a d d r e s s f i l t e r i n g Filter entriesMulticast address Filter registers Multicast address filtering exampleO c k s y n c h r o n i z a t i o n Multicast addressFiltering example Writing to other registersRegister address Filter Rxdptr EintrEintren TxptrH e r n e t G e n e r a l C o n t r o l R e g i s t e r # Address A060Enable RX packet processing Enable receive DMAEnable TX packet processing Accept short 64 receive framesEnable transmit DMA Enable initialization of RX buffer descriptorsEtxdma ErxinitMAC host interface soft reset RX Fifo RAM accessAlign RX data Insert transmit source addressH e r n e t G e n e r a l S t a t u s r e g i s t e r Rxinit H e r n e t T r a n s m i t S t a t u s r e g i s t e rRX initialization complete Frame transmitted OK Broadcast frame transmittedMulticast frame transmitted TX abort late collisionH e r n e t R e c e i v e S t a t u s r e g i s t e r Address A060 001CReceive frame size in bytes Receive frame OKReceive broadcast frame Receive multicast frameC C o n f i g u r a t i o n R e g i s t e r # Receive enable Bits Access Mnemonic Reset DefinitionInternal loopback Excess deferralAuto detect pad enable Vlan pad enablePad/CRC enable CRC enableC k t o B a c k I n t e r P a c k e t G a p r e g i s t e r PAD operation Table for transmitFrames TypeFull-duplex mode Half-duplex modeAddress A060 040C Back-to-back inter-packet-gapL l i s i o n W i n d o w / R e t r y r e g i s t e r Address A060IPGR1 Non back-to-back inter-packet-gap partX i m u m F r a m e r e g i s t e r CwinCollision window RetxMaximum frame length Reset MII management blockRmiim Clocks field Settings I M a n a g e m e n t C o m m a n d r e g i s t e rClock select Suppress preambleI M a n a g e m e n t a d d r e s s r e g i s t e r Register bitIf both Scan and Read are set, Scan takes precedence Automatically scan for read dataI M a n a g e m e n t R e a d D a t a r e g i s t e r I M a n a g e m e n t W r i t e D a t a r e g i s t e rAddress A060 042C I M a n a g e m e n t I n d i c a t o r s r e g i s t e r MII read dataMiilf MII link failureA t i o n a d d r e s s r e g i s t e r s Read data not validNvalid Automatically scan for read data in progressA t i o n a d d r e s s F i l t e r r e g i s t e r Register bit assignments for all three registersStation Address Register #1 Station Address Register #2G i s t e r H a s h T a b l e s PROPRM PRAAddress Register Transmit and receive counters A t i s t i c s r e g i s t e r sTR1K Receive statistics Counters address Receive byte counter A060 069CReceive packet counter A060 06A0 Address Register Receive countersReceive FCS error counter A060 06A4 Receive multicast packet counter A060 06A8Receive broadcast packet counter A060 06AC RbuoReceive alignment error counter A060 06BC Receive code error counter A060 06C4Receive carrier sense error counter A060 06C8 Receive undersize packet counter A060 06CCReceive jabber counter A060 06D8 Transmit statistics counters address mapTransmit byte counter A060 06E0 Address Register Transmit countersTransmit packet counter A060 06E4 Transmit excessive collision packet counter A060 Transmit oversize frame counter A060 Transmit undersize frame counter A060These are the General Statistics registers Carry RegisterC1MAX C1MGVC1RBY C1RPKMask register M1MGV M1RBYM1RPK M1RFCAddress A060 073C Mask register Register0x00000000 RXA Buffer Descriptor Pointer Address A060 0A04RXB Buffer Descriptor Pointer Address A060 0A08 Address A060 0A0CRXC Buffer Descriptor Pointer RXD Buffer Descriptor PointerH e r n e t I n t e r r u p t S t a t u s r e g i s t e r Address A060 0A10Rxovflstat RxbufcRxdoneb RxdonecRxdoned RxnobufH e r n e t I n t e r r u p t E n a b l e r e g i s t e r Address A060 0A14Address A060 0A18 Address A060 0A1C Address A060 0A20Address A060 0A24 Address A060 0A28 Address A060 0A2C Address A060 0A30Address A060 0A34 Address A060 0A38F r e e B u f f e r r e g i s t e r Address A060 0A3CRxfreed RxfreecL t i c a s t a d d r e s s F i l t e r r e g i s t e r s Address A060 0A58 Address A060 0A5CAddress A060 0A60 Address A060 0A64L t i c a s t a d d r e s s M a s k r e g i s t e r s Address A060 0A90 Address A060 0A94Address A060 0A98 Address A060 0A9CAddress A060 0AB4 Address A060 0AB8Address A060 0ABC Address A060 0AC0B u f f e r D e s c r i p t o r R a M Offset+0Offset+4 Offset+8Offset+C Address A060 2000 512 locationsM p l e h a s h t a b l e code Pointer to buffer to store hash table Pointer to hash table 337 Sample hash table code External DMA A t r a n s f e r sDMA buffer descriptor diagram A b u f f e r d e s c r i p t o rSource address pointer Buffer length DestinationS c r i p t o r l i s t p r o c e s s i n g Use this equation to compute total access time R i p h e r a l D M a r e a d a c c e s sDetermining the width of Pden Equation variables Variable DefinitionPeripheral DMA burst read access Peripheral DMA single read accessR i p h e r a l D M a w r i t e a c c e s s Peripheral DMA burst write access REQ signalREQ signal Logic remains paused until the REQ signal is reassertedDone signal Special circumstances Static ram chip select configurationA t i c R a M c h i p s e l e c t c o n f i g u r a t i o n Register name Field Value CommentA B u f f e r D e s c r i p t o r P o i n t e r A C o n t r o l r e g i s t e r Channel enable Channel goSource width Destination widthDestination burst Fly-by modeSource address increment State ResetIndex Error completion interrupt pending Normal completion interrupt pendingBuffer not ready interrupt pending Channel abort interrupt pendingA P e r i p h e r a l C h i p S e l e c t r e g i s t e r SEL Chip selectDMA Peripheral Chip Select register AES Processes 32 bits at a timeIs programmable for 128-, 192-, or 256-bit key lengths Supports ECB, CBC, OFB, CTR, and CCM cipher modesBlock diagram Key size Characteristic 128 192 256S D M a b u f f e r d e s c r i p t o r Data blocksAES buffer descriptor diagram Source address pointerSource buffer length Destination buffer lengthAES op code Interrupt I bit Last L bit Full F bitC r y p t i o n B p r o c e s s i n gC , C F B , O F B , a n d C T R p r o c e s s i n g CCM mode does not require an initialization vectorM m o d e Nonce buffer ContentsBits CCM mode Hub Module A c o n t r o l l e r AHB slaveInterface Servicing RX and FIFOsSource address pointer Buffer length Control15 W Control14Control13 L Control12 FControl110 Status150A n s m i t D M a e x a m p l e Not applicableProcess Pointer and IndexVisual example System MemoryReserved Uart a register Address mapUart B register Address map Register Offset DescriptionUart C register Address map Uart D register Address mapSPI register Address map AD register Address mapReserved I2C register Address mapIO Hardware Assist register RTC register Address mapIO register Address map Error completion interrupt pending RX Normal completion interrupt pending RXBuffer not ready interrupt pending RX Channel abort interrupt pending RXRX Fifo service request interrupt pending Error completion interrupt pending TXTX Fifo service request interrupt pending RX Fifo overflow interrupt pendingD u l e D M a R X C o n t r o l Flex I/O Channel abortDirect Rxthrs RxbdpRX Fifo threshold D u l e D i r e c t M o d e R X S t a t u s F I F O D u l e D i r e c t M o d e R X D a t a F I F O Full flagD u l e D M a T X C o n t r o l IndexenTxbdp D u l e D i r e c t M o d e T X D a t a F I F O TX Fifo thresholdTXD D u l e D i r e c t M o d e T X D a t a L a s t F I F OTxdl 384 Modem control signal support Receive error conditionsCharacter gap timeout DMA transfers to and from system memoryExample configuration R m a l m o d e o p e r a t i o nUart module structure Control register Field Value CommentU d r a t e g e n e r a t o r Baud ratesThis table shows the baud rates achieved with CLKref set to Divisor Baud rateR d w a r e b a s e d f l o w c o n t r o l R c e d c h a r a c t e r t r a n s m i s s i o nForce character transmission procedure Collecting feedback M w a k e u p o n c h a r a c t e r r e c o g n i t i o nA p p e r C o n t r o l a n d S t a t u s r e g i s t e r s Address RegisterDLAB=0 DLAB=1A p p e r C o n f i g u r a t i o n r e g i s t e r RtsenRTS DtrenSoftware Receive character-based flow controlRemote loopback RTS controlEnable force complete T e r r u p t E n a b l e r e g i s t e rRS485 transceiver deassertion control RS485 transceiver assertion controlEnable overflow error Enable parity errorEnable frame error Enable line breakT e r r u p t S t a t u s r e g i s t e r Parity error Frame errorUart interrupt Force completeRing indicator Character match3Character match2 Character match1Enable receive character gap timer Transmit idleReceive idle Write this field toEnable transmit bit rate generation C e i v e B u f f e r G a P C o n t r o l r e g i s t e rMask Enable character matchData Flow control enable FlowstateFlow control state FLOW4FLOW2 Force transmit enable M W a k e u p C o n t r o l r e g i s t e rRead-only busy CharEnable A n s m i t B y t e C o u n tAddress 90011034 / 90019034 / 90021034 TxcountR T T r a n s m i t B u f f e r R T R e c e i v e B u f f e rRbuff R T B a u d R a t e D i v i s o r L S B R T B a u d R a t e D i v i s o r M S BTbuff BrdlEnables modem status interrupt R T I n t e r r u p t E n a b l e r e g i s t e rBrdm EdssiEnables receive line status interrupt Enables transmit holding register empty interruptEnables receive data available interrupt Interrupt identificationEnable the TX and RX Fifo R T F I F O C o n t r o l r e g i s t e rR T L i n e C o n t r o l r e g i s t e r Clear all bytes in the TX FifoDivisor latch access bit Parity enableSet break, if set TX data is set to Stick parity, operates as followsLocal loopback enable bit R T M o d e m C o n t r o l r e g i s t e rR T L i n e S t a t u s r e g i s t e r Automatic flow controlR T M o d e m S t a t u s r e g i s t e r Delta DCD indicator Trailing edge of RI indicatorDelta DSR indicator Delta CTS indicatorUart Modem Status register C e i v e a n d t r a n s m i t o p e r a t i o n s Hdlc module structureO c k i n g T sTransmit operation Transmitter underflowT a e n c o d i n g Last byte bit Pattern tableEncoding examples Last byte bit pattern Valid dataTransitions Dpll operation Adjustment ranges and output clocks NRZ and Nrzi encoding Biphase-Level encoding CLK Address Received or a buffer close event occurs, such as end Enable Hdlc interrupt Enable invalid CRCEnable valid CRC Local loopbackEnable receive abort error RabortReceive abort error Hdlc interruptInvalid CRC Valid CRCL C D a t a R e g i s t e r HdataHdata Hmode L C C o n t r o l R e g i s t e rClock source L C C l o c k D i v i d e r L o w Address 9002911C L C C l o c k D i v i d e r H i g hDivl Clock enable DivhFour-wire interface RXD, TXD, CLK, CS Programmable SPI mode 0, 1, 2, orMaster mode internal diagnostic loopback Interface SPI moduleI c o n t r o l l e r SPI module structureTiming modes Clocking mode diagrams SPI mode SPI CLK IdleI c l o c k i n g m o d e s Capture edge Drive edgeSPI master mode SPI slave mode I c l o c k g e n e r a t i o nS t e m b o o t o v e r S P I o p e r a t i o n Clock generation samplesBootmode10 Address width Available Strapping optionsEEPROM/FLASH header Entry NameTime to completion Entry Name DescriptionConfiguration registers for the SPI module are located at This is the primary SPI Configuration registerEnable master loopback mode I C o n t r o l a n d S t a t u s r e g i s t e r sSPI mode Slave enableO c k G e n e r a t i o n r e g i s t e r Discard bytesBits Access Mnemonic Reset Divisor Enable clock generationRegister programming steps Use this register to define the data rate of the interfaceD3102 Not used Write this field to D01 SPI master timing Parameters I t i m i n g c h a r a c t e r i s t i c sParm Description Min Max Unit SPI master timing diagram SPI slave timing parameters SPI slave timing diagram SPI timing characteristics Interface timing, data structure, and error handling Y s i c a l I 2 C b u sI2C bus OverviewE x t e r n a l a d d r e s s e s Slave Description Addres BitCommand Name Description C o m m a n d i n t e r f a c eR e g i s t e r s M m a n d T r a n s m i t D a t a r e g i s t e rAddress 9005 RegisterDescription2C Dlen port iicdlen A t u s R e c e i v e D a t a r e g i s t e rProvide new transmit data S t e r a d d r e s s r e g i s t e r ScmdlMcmdl IrqcdA v e a d d r e s s r e g i s t e r Timing parameter for fast-mode Register Address 9005 000CMask the interrupt to the ARM CPU irqdis Master/slave interrupt codes T e r r u p t codesCode Name Master/slave Description F t w a r e d r i v e r I2C master software driver I2C slave high level driverO w c h a r t s Master module normal mode, 16- bitSlave module normal mode, 16- bit Real Time Clock Module C G e n e r a l C o n t r o l r e g i s t e r Address 900612/24 clock mode operation 2 4 H o u r r e g i s t e rCalendar operation Time date, hour, minute, second operationHRT M e r e g i s t e rHRU L e n d a r r e g i s t e r Address 9006 000CM e Alarm r e g i s t e r L e n d a r Alarm r e g i s t e r Alarm E n a b l e r e g i s t e rE n t F l a g s r e g i s t e r Address 9006 001CAlarm event Month eventDate event Hour eventAlarm interrupt Month interruptDate interrupt Hour interruptT e r r u p t D i s a b l e r e g i s t e r T e r r u p t E n a b l e S t a t u s r e g i s t e r N e r a l S t a t u s r e g i s t e r Address 9006 002CGeneral Status register ADC module StructureC D M a p r o c e d u r e ADC control blockC c o n t r o l a n d s t a t u s r e g i s t e r s ADC configuration registers are located at offsetC C o n f i g u r a t i o n r e g i s t e r Interrupt status DMA enableADC channel select C O u t p u t R e g i s t e r s 0 C C l o c k C o n f i g u r a t i o n r e g i s t e rWait Dout E c t r i c a l c h a r a c t e r i s t i c s Parameter Symbola Rating UnitAbsolute maximum ratings CPU / Memory clock Power Parameter Symbol a Rating UnitRecommended operating conditions Inputs E l e c t r i c a l c h a r a c t e r i s t i c sSym Parameter Conditiona Value Unit Ouputs Sym Parameter Value UnitManufacturer Part Number Description NC7SP1774LVC1G17GW SN74LVC1G17DCM o r y T i m i n g Sdram burst read 16-bit Sdram burst read 16 bit, CAS latency = Sdram burst write 16 bit Sdram burst read 32 bit Sdram burst read 32 bit, CAS latency = Sdram burst write 32-bit Sdram load mode Sdram refresh mode Clock enable timing Parm Description Min Max Unit Static RAM read cycles with 0 wait states Static RAM asynchronous page mode read, Wtpg = Static RAM read cycle with configurable wait states Static RAM sequential write cycles Static RAM write cycle Static write cycle with configurable wait states Slow peripheral acknowledge timing CPUSlow peripheral acknowledge read Slow peripheral acknowledge writeEthernet timing Ethernet MII timingStandard Mode Fast Mode Parm Description Min Max Unit I2C timingSPI Timing Parm Description Min Max Unit Mod NotSPI master parameters SPI slave parametersTbclk *8 SPI master mode 0 and 1 2-byte transfer SPI master mode2 and 3 2-byte transferSPI slave mode 0 and 1 2-byte transfer SPI slave mode 2 and 3 2-byte transferS e t a n d h a r d w a r e s t r a p p i n g t i m i n g Parm Description Min Typ UnitA G t i m i n g O c k t i m i n g Diagram below pertains to clock timingSystem PLL reference clock Timing Clock timing Packaging C k a g eO c e s s o r D i m e n s i o n s C K a G I N G Processor Dimensions V i s i o n B V i s i o n C