Digi NS9215 manual DCD Uart a, CTS Uart a, DSR Uart a, RXD Uart a, RI Uart a, TXC / DTR Uart a

P I N O U T ( 2 6 5 )

General purpose I/O (GPIO)

Note: All GPIOs except 12 and 16 to 31 are reset to mode 3, input. GPIO 12 is reset to mode 2, reset_done. GPIO 16 to 31 are reset to mode 0, external memory data 15:0.

Pin	Signal	U/D	I/O	OD	Description
K15	gpio[0]	U	I/O	2	0	DCD UART A
					1	Ext DMA Done Ch 0
					2	PIC_0_GEN_IO[0](I/O)
					3	gpio[0]
					4	SPI EN (dup)
K17	gpio[1]	U	I/O	2	0	CTS UART A
					1	Ext Int 0
					2	PIC_0_GEN_IO[1](I/O)
					3	gpio[1]
					4	Reserved
J17	gpio[2]	U	I/O	2	0	DSR UART A
					1	Ext Int 1
					2	PIC_0_GEN_IO[2](I/O)
					3	gpio[2]
					4	Reserved
J16	gpio[3]	U	I/O	2	0	RXD UART A
					1	Ext DMA Pden Ch 0
					2	PIC_0_GEN_IO[3](I/O)
					3	gpio[3]
					4	SPI RXD (dup)
H17	gpio[4]	U	I/O	2	0	RI UART A
					1	Ext Int Ch 2
					2	Ext Timer Event In Ch 6
					3	gpio[4]
					4	SPI CLK (dup)
H13	gpio[5]	U	I/O	2	0	RTS / RS485 Control UART A
					1	Ext Int Ch 3
					2	Ext Timer Event Out Ch 6
					3	gpio[5]
					4	SPI CLK (dup)
H14	gpio[6]	U	I/O	2	0	TXC / DTR UART A
					1	Ext DMA Req Ch 0
					2	Ext Timer Event In Ch 7
					3	gpio[6]
					4	PIC_DBG_DATA_OUT(O)
G14	gpio[7]	U	I/O	2	0	TXD UART A
					1	Ext Timer Event In Ch 8
					2	Ext Timer Event Out Ch 7
					3	gpio[7]
					4	SPI TXD (dup)

32Hardware Reference NS9215