E X T E R N A L D M A

. .

 

 

 

Descriptor list processing..

 

 

.

 

Note: Optimal performance is achieved when the destination address is aligned on a

 

word boundary.

 

Status

This field is not used. Read back 0x0000.

 

Wrap (W) bit

The Wrap (W) bit, when set, tells the DMA controller that this is the last buffer

 

 

descriptor within the continuous list of descriptors. The next buffer descriptor is

 

 

found using the initial DMA channel buffer descriptor pointer. When the W bit is not

 

set, the next buffer descriptor is found using an offset of 0x10 from the current

 

 

buffer descriptor.

 

Interrupt (I) bit

The Interrupt (I) bit, when set, tells the DMA controller to issue an interrupt to the

 

CPU when the buffer is closed due to a normal channel completion. The interruption

 

occurs regardless of the normal completion interrupt enable configuration for the

 

 

DMA channel.

 

Last (L) bit

The Last (L) bit, when set, tells the DMA controller that this buffer descriptor is the

 

last descriptor that completes an entire message frame. The DMA controller uses this

 

bit to assert the normal channel completion status when the byte count reaches zero.

Full (F) bit

The Full (F) bit, when set, indicates that the buffer descriptor is valid and can be

 

 

processed by the DMA channel. The DMA channel clears this bit after completing the

 

transfer(s).

 

The DMA channel does not try a transfer with the F bit clear. The DMA channel enters an idle state upon fetching a buffer descriptor with the F bit cleared. Whenever the F bit is modified by the device driver, the device driver must also write a 1 to the CE bit in the DMA Control register to activate the idle channel.

D e s c r i p t o r l i s t p r o c e s s i n g

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Once a DMA controller has completed the operation specified by the current buffer descriptor, it clears the F bit and fetches the next buffer descriptor. A DMA channel asserts the NRIP field (buffer not ready interrupt pending) in the DMA Status register and returns to the idle state upon fetching a buffer descriptor with the F bit in the incorrect state. A DMA channel always closes the current descriptor and moves on to the next descriptor when a DMA transfer is terminated by the assertion of the DONE signal.

www.digiembedded.com

341

Page 341
Image 341
Digi NS9215 manual S c r i p t o r l i s t p r o c e s s i n g

NS9215 specifications

The Digi NS9215 is a powerful solution designed for industrial applications that require reliable connectivity and robust performance. Built on a foundation of advanced technologies, the NS9215 serves as a versatile networking device that meets the demands of automation, remote monitoring, and data acquisition.

One of the standout features of the Digi NS9215 is its multi-protocol support. It is capable of handling various communication protocols, including Ethernet, Serial, and Wireless, making it ideal for integration into heterogeneous environments. This flexibility enables users to connect legacy devices to modern networks seamlessly, facilitating smoother data communication across different platforms.

The NS9215 is equipped with powerful processing capabilities, featuring an integrated processor that ensures efficient data handling. This enables the device to perform complex data tasks without compromising performance. Its high-speed connectivity options also allow for rapid data transmission, which is crucial for real-time applications in industrial settings.

Another critical characteristic of the Digi NS9215 is its reliability in harsh environments. Built to withstand extreme temperatures, humidity, and electrical interference, this device assures consistent operation even in challenging conditions. Its rugged design minimizes the risk of failure, making it suitable for deployment in various industrial environments.

Security is a top priority for the Digi NS9215. It comes with advanced security features that protect sensitive data during transmission and prevent unauthorized access. Employing encryption protocols and secure authentication methods, the NS9215 ensures that data integrity and confidentiality are maintained throughout its operation.

The user-friendly interface of the NS9215 allows for easy configuration and management. This ease of use reduces the time required for installation and setup, enabling quick deployment in field operations. Additionally, remote management capabilities enhance operational efficiency, allowing users to monitor device performance and make adjustments from anywhere.

Furthermore, the NS9215 supports extensive scalability options. As organizations grow and evolve, the ability to scale up or adapt the networking capabilities becomes essential. With its modular design, the NS9215 can easily accommodate additional devices and protocols, ensuring longevity and continued relevance in a rapidly changing technological landscape.

In conclusion, the Digi NS9215 is a robust networking device designed for a wide range of industrial applications. Its multi-protocol support, reliability, security features, user-friendly interface, and scalability make it a valuable addition to any industrial network infrastructure, delivering performance and efficiency that businesses can depend on for critical operations.