Level Two Interface

 

 

Table 9-4 Non-cacheable LDRB (continued)

 

 

 

 

 

Address[2:0]

ARADDRM

ARBURSTM

ARSIZEM

ARLENM

 

 

 

 

 

0x4 (byte 4)

0x04

Incr

8-bit

1 data transfer

 

 

 

 

 

0x5 (byte 5)

0x05

Incr

8-bit

1 data transfer

 

 

 

 

 

0x6 (byte 6)

0x06

Incr

8-bit

1 data transfer

 

 

 

 

 

0x7 (byte 7)

0x07

Incr

8-bit

1 data transfer

 

 

 

 

 

LDRH

Table 9-5shows the values of ARADDRM, ARBURSTM, ARSIZEM, and ARLENM for a Non-cacheable LDRH from halfwords 0-3 in Strongly Ordered or Device memory.

Table 9-5 LDRH from Strongly Ordered or Device memory

Address[3:0]

ARADDRM

ARBURSTM

ARSIZEM

ARLENM

 

 

 

 

 

0x0 (halfword 0)

0x00

Incr

16-bit

1 data transfer

 

 

 

 

 

0x2 (halfword 1)

0x02

Incr

16-bit

1 data transfer

 

 

 

 

 

0x4 (halfword 2)

0x04

Incr

16-bit

1 data transfer

 

 

 

 

 

0x6 (halfword 3)

0x06

Incr

16-bit

1 data transfer

 

 

 

 

 

Note

A load of a halfword from Strongly Ordered or Device memory addresses 0x1, 0x3, 0x5, or 0x7 generates an alignment fault.

LDR or LDM that transfers one register

Table 9-6shows the values of ARADDRM, ARBURSTM, ARSIZEM, and ARLENM for a Non-cacheable LDR or an LDM that transfers one register, (an LDM1) in Strongly Ordered or Device memory.

Table 9-6 LDR or LDM1 from Strongly Ordered or Device memory

Address[2:0]

ARADDRM

ARBURSTM

ARSIZEM

ARLENM

 

 

 

 

 

0x0 (word 0)

0x00

Incr

32-bit

1 data transfer

 

 

 

 

 

0x4 (word 1)

0x04

Incr

32-bit

1 data transfer

 

 

 

 

 

Note

A load of a word from Strongly Ordered or Device memory addresses 0x1, 0x2, 0x3, 0x5, 0x6, or 0x7 generates an alignment fault.

ARM DDI 0363E

Copyright © 2009 ARM Limited. All rights reserved.

9-9

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ARM r1p3, R4F manual LDR or LDM that transfers one register, Ldrh from Strongly Ordered or Device memory Address30