ARM r1p3, R4F manual Chapter AC Characteristics

			Contents
	11.4	Debug register descriptions	11-10
	11.5	Management registers	11-32
	11.6	Debug events	11-39
	11.7	Debug exception	11-41
	11.8	Debug state	11-44
	11.9	Cache debug	11-50
	11.10	External debug interface	11-51
	11.11	Using the debug functionality	11-54
	11.12	Debugging systems with energy management capabilities	11-71
Chapter 12	FPU Programmer’s Model
	12.1	About the FPU programmer’s model	12-2
	12.2	General-purpose registers	12-3
	12.3	System registers	12-4
	12.4	Modes of operation	12-10
	12.5	Compliance with the IEEE 754 standard	12-11
Chapter 13	Integration Test Registers
	13.1	About Integration Test Registers	13-2
	13.2	Programming and reading Integration Test Registers	13-3
	13.3	Summary of the processor registers used for integration testing	13-4
	13.4	Processor integration testing	13-5
Chapter 14	Cycle Timings and Interlock Behavior
	14.1	About cycle timings and interlock behavior	14-3
	14.2	Register interlock examples	14-6
	14.3	Data processing instructions	14-7
	14.4	QADD, QDADD, QSUB, and QDSUB instructions	14-9
	14.5	Media data-processing	14-10
	14.6	Sum of Absolute Differences (SAD)	14-11
	14.7	Multiplies	14-12
	14.8	Divide	14-14
	14.9	Branches	14-15
	14.10	Processor state updating instructions	14-16
	14.11	Single load and store instructions	14-17
	14.12	Load and Store Double instructions	14-20
	14.13	Load and Store Multiple instructions	14-21
	14.14	RFE and SRS instructions	14-24
	14.15	Synchronization instructions	14-25
	14.16	Coprocessor instructions	14-26
	14.17	SVC, BKPT, Undefined, and Prefetch Aborted instructions	14-27
	14.18	Miscellaneous instructions	14-28
	14.19	Floating-point register transfer instructions	14-29
	14.20	Floating-point load/store instructions	14-30
	14.21	Floating-pointsingle-precision data processing instructions	14-32
	14.22	Floating-pointdouble-precision data processing instructions	14-33
	14.23	Dual issue	14-34
Chapter 15	AC Characteristics
	15.1	Processor timing	15-2
	15.2	Processor timing parameters	15-3
Appendix A	Processor Signal Descriptions
	A.1	About the processor signal descriptions	A-2
	A.2	Global signals	A-3
	A.3	Configuration signals	A-4
	A.4	Interrupt signals, including VIC interface signals	A-7
	A.5	L2 interface signals	A-8
	A.6	TCM interface signals	A-13

ARM DDI 0363E	Copyright © 2009 ARM Limited. All rights reserved.	v
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