Cortex-R4 and Cortex-R4F
Technical Reference Manual
Cortex-R4 and Cortex-R4F
Copyright 2009 ARM Limited. All rights reserved
Chapter Introduction
Cortex-R4 and Cortex-R4F Technical Reference Manual
Chapter Processor Initialization, Resets, and Clocking
Chapter AC Characteristics
Appendix B ECC Schemes
List of Tables
Adfsr and Aifsr bit functions
Dirty register format, with ECC
11-12
Example interlocks 14-11
Table A-18 FPU signals Table C-1
List of Figures
Cache operations C7 format for Set and Way
Vector Catch Register format 11-20
Feedback on
Preface
About this book
Using this book
Product revision status
Identifies the major revision of the product
Typographical
Conventions
Signals
Timing diagrams
This section lists publications by ARM and by third parties
Further reading
ARM publications
Other publications
ARM welcomes feedback on this product and its documentation
Feedback
Feedback on this product
Feedback on this book
Introduction
About the processor
About the architecture
This section describes the main components of the processor
Components of the processor
Debug on
System control coprocessor on Interrupt handling on
Floating Point Unit
Data Processing Unit
Load/store unit
Prefetch unit
Memory Protection Unit
Instruction and data caches
TCM interfaces
5 L2 AXI interfaces
Error correction and detection
AXI master interface
AXI slave interface
System performance monitoring
Debug
ETM interface
Real-time debug facilities
Interrupt handling
System control coprocessor
VIC port
Low interrupt latency
Changes
Return from exception using data from the stack
External interfaces of the processor
Processor has the following interfaces for external access
APB Debug interface ETM interface Test interface
APB Debug interface
Run mode
Power management
Standby mode
Shutdown mode
Configurable options
Configurable options
Atcm
VFP
Btcm
FPU includeda
MPU
Atcmpcen
Configurable options at reset Feature Options Register
B0TCMPCEN
B1TCMPCEN
B0TCMECEN
Atcmecen
B1TCMECEN
Atcmrmw
Names of the pipeline stages and their functions are
Execution pipeline stages
Instruction decode
Iss
First stage of data memory access
Execute stages
Write-back of data from the execution pipelines
Redundant core comparison
Test features
Documentation
Product documentation, design flow, and architecture
Design flow
Configuration inputs
Build configuration
Software configuration
Architectural information
Advanced Microcontroller Bus Architecture protocol
Processor identification
Product revision information
Revision field, Main ID Register
Variant field, Main ID Register
Variant field, Debug ID Register
Revision field, Debug ID Register
Registers on
Programmer’s Model
Program status registers on
Exceptions on
About the programmer’s model
Instruction set states
Switching state
ARM state
Thumb state
Operating modes
Data types
Byte-invariantbig-endian format Little-endian format
Memory formats
Byte-invariant big-endian format
Little-endian format
Register set
Registers
Register mode identifiers Mode Mode identifier
General registers and program counter
N, Z, C, and V bits
Program status registers
IT bits
Q bit
DNM bits
J bit
GE bits
A bit
E bit
I and F bits
Non-maskable fast interrupts on
M40 Mode Visible state registers Thumb
PSR mode bit values
M bits
Modification of PSR bits by MSR instructions
ARM DDI 0363E
Exceptions
Reset on Interrupts on Aborts on
Exception entry and exit summary
Exception entry and exit summary
Leaving an exception
Taking an exception
Interrupts
Reset
Interrupt request
Program status registers on Non-maskable fast interrupts
Fast interrupt request
Non-maskable fast interrupts
Interrupt controller
Interrupt entry flowchart
Interrupt entry sequence
Prefetch aborts
Aborts
Data aborts
Precise aborts
Aborts in Strongly Ordered and Device memory
Imprecise aborts
Supervisor call instruction
Abort handler
Breakpoint instruction
Undefined instruction
Exception vectors
Acceleration of execution environments
Architecture Reference Manual
Unaligned and mixed-endian data access support
Big-endian instruction support
Resets on
Processor Initialization, Resets, and Clocking
Reset modes on
Initialization on
Caches on TCM on
Initialization
1 MPU
2 CRS
5 TCM
Caches
Preloading TCMs
Write to TCM directly from debugger
DMA into TCM
Preloading TCMs with parity or ECC
Using TCMs from reset
NRESET
Resets
PRESETDBGn
NSYSPORESET
Power-on reset
Reset modes
Normal operation
Processor reset
Halt operation
AXI interface clocking Clock gating
Clocking
AXI interface clocking
Clock gating
System Control Coprocessor
System control coprocessor functional groups
About the system control coprocessor
Function Register/operation Reference to description
System control coprocessor register functions
Fcse PID
Configuration Region
System control and configuration
TCM control TCM Status
System performance Performance monitoring
Cache control and configuration
MPU control and configuration
System performance monitor
TCM control and configuration
System performance monitor registers
System validation
ARM DDI 0363E
Register allocation
System control coprocessor registers
RAZ
Undefined MPU Region Size Read/write
Enable Undefined MPU Region Access Read/write
Control Undefined MPU Memory Region Read/write
Number
ARM DDI 0363E
Event Select Read/write Unpredictable Performance Monitor
Undefined C3-c11 C12 Performance Monitor Read/write
Count Undefined
Undefined C1-c15 C12 C0-c15 C13
C14 User Enable Read/write
RAZ,ignore
Writes Context ID Read/write
7shows the arrangement of bits in the register
2 c0, Main ID Register
Main ID Register bit functions
3 c0, Cache Type Register
Bits Field Function
4 c0, TCM Type Register
To access the Cache Type Register, read CP15 with
Cache Type Register bit functions Bits Field Function
TCM Type Register bit functions Bits Field Function
To access the MPU Type Register, read CP15 with
To access the TCM Type Register, read CP15 with
5 c0, MPU Type Register
TCM Type Register bit functions
C0, Processor Feature Register 0, PFR0
Processor Feature Registers
6 c0, Multiprocessor ID Register
C0, Processor Feature Register 1, PFR1
To access the Processor Feature Register 0 read CP15 with
Processor Feature Register 0 bit functions
Processor Feature Register 1 bit functions
8 c0, Debug Feature Register
To access the Processor Feature Register 1 read CP15 with
Debug Feature Register 0 bit functions
3124 Reserved
9 c0, Auxiliary Feature Register
To access the Debug Feature Register 0 read CP15 with
Memory Model Feature Registers
C0, Memory Model Feature Register 0, MMFR0
10 Memory Model Feature Register 0 bit functions
C0, Memory Model Feature Register 1, MMFR1
11 Memory Model Feature Register 1 bit functions
16 Memory Model Feature Register 1 format
WFI
C0, Memory Model Feature Register 2, MMFR2
DMB
13 Memory Model Feature Register 3 bit functions
C0, Memory Model Feature Register 3, MMFR3
3112 Reserved
C0, Instruction Set Attributes Register 0, ISAR0
Instruction Set Attributes Registers
14 Instruction Set Attributes Register 0 bit functions
20 Instruction Set Attributes Register 1 format
C0, Instruction Set Attributes Register 1, ISAR1
ITE
C0, Instruction Set Attributes Register 2, ISAR2
Indicates support for if then instructions
PSR
16 Instruction Set Attributes Register 2 bit functions
Indicates support for PSR instructions
17 Instruction Set Attributes Register 3 bit functions
C0, Instruction Set Attributes Register 3, ISAR3
Thumb instruction sets
23 Instruction Set Attributes Register 4 format
C0, Instruction Set Attributes Register 4, ISAR4
12 c0, Current Cache Size Identification Register
C0, Instruction Set Attributes Registers
18 Instruction Set Attributes Register 4 bit functions
8KB
4KB
3130 Reserved
13 c0, Current Cache Level ID Register
15 c1, System Control Register
14 c0, Cache Size Selection Register
AFE
23 System Control Register bit functions
TRE
Nmfi
= data caching disabled. This is the reset value
Enables L1 data cache
= data caching enabled
= strict alignment fault checking enabled
C1, Auxiliary Control Register
Auxiliary Control Registers
24 Auxiliary Control Register bit functions
Axiscuen
Axiscen
Dilsm
Deolp
Dbwr
Rsdis
Dlfo
Dnch
C15, Secondary Auxiliary Control Register
25 Secondary Auxiliary Control Register bit functions
IXC
Doofmacs
OFC
UFC
Primary input RMWENRAM1 defines the reset value
17 c1, Coprocessor Access Register
Primary input RMWENRAM0 defines the reset value
Atcmecc
C5, Data Fault Status Register
Fault Status and Address Registers
All other encodings for these FSR bits are Reserved
28 Data Fault Status Register bit functions
C5, Instruction Fault Status Register
To use the Dfsr read or write CP15 with
C5, Auxiliary Fault Status Registers
To access the Ifsr read or write CP15 with
There are two auxiliary fault status registers
29 Instruction Fault Status Register bit functions
30 Adfsr and Aifsr bit functions
C6, Data Fault Address Register
= Atcm
= Btcm
19 c6, MPU memory region programming registers
C6, Instruction Fault Address Register
C6, MPU Region Base Address Registers
C6, MPU Region Size and Enable Registers
158 Sub-region disable
C6, MPU Region Access Control Registers
32 Region Size Register bit functions
TEX
33 MPU Region Access Control Register bit functions
C6, MPU Memory Region Number Register
34 Access data permission bit encoding
UNP
35 MPU Memory Region Number Register bit functions
Point of Coherency PoC
Cache operations
Point of Unification PoU
Set and Way format
Invalidate and clean operations
Address format
37shows the cache sizes and the resultant bit range for Set
36 Functional bits of c7 for Set and Way
37 Widths of the set field for L1 cache sizes Size Set
Data Memory Barrier operation
Data Synchronization Barrier operation
21 c9, Btcm Region Register
38 Functional bits of c7 for address format Bits Field
22 c9, Atcm Region Register
To access the Btcm Region Register, read or write CP15 with
39 Btcm Region Register bit functions
23 c9, TCM Selection Register
To access the Atcm Region Register, read or write CP15 with
24 c11, Slave Port Control Register
40 Atcm Region Register bit functions
26 c13, Context ID Register
25 c13, Fcse PID Register
312 Reserved
RAZ/UNP
27 c13, Thread and Process ID Registers
Validation Registers
C15, nVAL IRQ Enable Set Register
Ccnt overflow IRQ request
Ccnt overflow FIQ request
C15, nVAL FIQ Enable Set Register
C15, nVAL Debug Request Enable Set Register
C15, nVAL Reset Enable Set Register
Ccnt overflow reset request
Ccnt overflow debug request
C15, nVAL IRQ Enable Clear Register
48 nVAL IRQ Enable Clear Register format
C15, nVAL FIQ Enable Clear Register
303 Reserved UNP or Sbzp
C15, nVAL Reset Enable Clear Register
51 nVAL Debug Request Enable Clear Register format
C15, nVAL Debug Request Enable Clear Register
50 nVAL Cache Size Override Register
C15, nVAL Cache Size Override Register
318 Reserved
B0000 4kB B0001 8kB B0011 16kB B0111 32kB B1111 64kB
53 Correctable Fault Location Register cache
Correctable Fault Location Register
52 Correctable Fault Location Register cache
Build Options Registers
To access the Build Options 1 Register, write CP15 with
C15, Build Options 1 Register
C15, Build Options 2 Register
Noicache
55 Build Options 2 Register
Nodcache
Atcmes
Noie
Btcmes
Nofpu
Nompu
Noharderrorcach
To access the Build Options 2 Register, write CP15 with
Dcachees
Axibusparity
Prefetch Unit
About the prefetch unit
Disabling program flow prediction
Branch prediction
Branch predictor
Configuring the branch predictor
Incorrect predictions and correction
Return stack
Events and Performance Monitor
About the events
Bit position Update Value
Event bus interface bit functions
Event
ETMEXTOUT1
ETMEXTOUT0
Instruction cache access
Non-cacheable access on AXI master bus
But with different attributes Dual issue case a branch
Dual issue case B1, B2, F2 load/store, F2D
TCM correctable ECC error reported by prefetch unit Yes
TCM correctable ECC error reported by load/store unit Yes
About the PMU
Performance monitoring registers are described
Performance monitoring registers
1 c9, Performance Monitor Control Register
2shows how the bit values correspond with the Pmnc Register
Pmnc Register bit functions
2 c9, Count Enable Set Register
3 c9, Count Enable Clear Register
To access the Cntens Register, read or write CP15 with
Cntens Register bit functions Bits Field Function
Cycle counter enable clear
To access the Cntenc Register, read or write CP15 with
4 c9, Overflow Flag Status Register
Cntenc Register bit functions Bits Field Function
5shows how the bit values correspond with the Flag Register
To access the Flag Register, read or write CP15 with
5 c9, Software Increment Register
6 c9, Performance Counter Selection Register
To access the Swincr Register, read or write CP15 with
Swincr Register bit functions Bits Field Function
313 Reserved RAZ on reads, Sbzp on writes Increment Counter
8 c9, Event Selection Register
7 c9, Cycle Count Register
SEL
EVTSELx Register bit functions
To access the EVTSELx Register, read or write CP15 with
9 c9, Performance Monitor Count Registers
10 c9, User Enable Register
Useren Register bit functions
Ccnt overflow interrupt enable
11 c9, Interrupt Enable Set Register
10 Intens Register bit functions Bits Field Function
Ccnt overflow interrupt enable bit
12 c9, Interrupt Enable Clear Register
11 Intenc Register bit functions Bits Field Function
To access the Intenc Register, read or write CP15 with
Use of the event bus and counters
Event bus interface
MPU software-accessible registers on
MPU faults on
Memory Protection Unit
About the MPU
Default memory map
True
Region base address
Memory regions
Region size
Subregions
Region attributes
Region access permissions
Overlapping regions
Region
Example of using subregions
Example of using regions that overlap
TCM regions
Background regions
Memory types
Using memory types
ARM DDI 0363E
TEX20, C, and B encodings Description Memory Type Shareable?
Region attributes
1BB
Cacheable memory policies
MPU interaction with memory system
On page 7-2shows the default memory map
Following code is an example of disabling the MPU
Background fault Permission fault Alignment fault
MPU faults
Background fault
Permission fault
On page 4-5shows the CP15 registers that control the MPU
MPU software-accessible registers
Level One Memory System
About the L1 memory system
L1 memory system block diagram
Parity Bit ECC on
About the error detection and correction schemes
Parity
Hard errors
Error checking and correction
Bit ECC
Read-Modify-Write
Correct inline
Error correction
Correct-and-retry
Faults
Fault handling
Classes of fault that can occur are
MPU faults
Cache and TCM parity and ECC errors
External faults
TCM external faults
Debug events
Fault status information
Precise and imprecise aborts
Abort exceptions
Imprecise abort exceptions
Precise abort exceptions
Usage models
Types of aborts Conditions Source Precise Fatal
Correctable errors
AXI
ARM DDI 0363E
TCM attributes and permissions
About the TCMs
TCM internal error detection and correction
Atcm and Btcm configuration
Handling TCM parity errors on Handling TCM ECC errors on
Handling TCM ECC errors
Handling TCM parity errors
TCM arbitration
TCM initialization
External TCM errors
TCM port protocol
AXI slave interfaces for TCMs
Store buffer
About the caches
Store buffer merging
Cache maintenance operations
Store buffer behavior
Store buffer draining
Error build options
Cache error detection and correction
Handling cache parity errors
Address decoder faults
Cache parity error behavior Value Behavior
Cache ECC error behavior Value Behavior
Handling cache ECC errors
Errors on data cache read
Errors on instruction cache read
Errors on data cache write
Errors on evictions
Invalidate all instruction cache
Clean data cache by set/way
Tag RAM
Cache RAM organization
Dirty RAM on Data RAM on
Tag RAM
Data RAM
Dirty RAM
Cache sizes and tag RAM organization Tag RAM organization
Organization of a dirty RAM line
Nonsequential read operation performed with one RAM access
Data RAM sizes without parity or ECC implemented
13 Data cache RAM bits, with parity Description
Disabling or enabling all of the caches
Cache interaction with memory system
Following code is an example of enabling caches
15 Data cache data RAM sizes with ECC Cache size Data RAMs
Disabling or enabling instruction cache
Disabling or enabling error checking
Disabling or enabling data cache
MCR p15 R0, c1 Write System Control Register
Internal exclusive monitor
Memory types and L1 memory system behavior
TCM error events
Error detection events
Instruction-cache error events
Data-cache error events
ARM DDI 0363E
Level Two Interface
About the L2 interface
1shows the AXI master interface attributes
AXI master interface
Attribute Value Comments
Outstanding write/read access on different IDs
Identifiers for AXI bus accesses
Outstanding write accesses with the same ID
Write response
Memory attributes
Eviction buffer
Arcachem and Awcachem encodings Encoding a Meaning
Aruserm and Awuserm encodings
Memory system implications for AXI accesses
Strongly Ordered and Device transactions on
AXI master interface transfers
Linefills on
Strongly Ordered and Device transactions
Restrictions on AXI transfers
Non-cacheable Ldrb
Address20
Ldrh from Strongly Ordered or Device memory Address30
LDR or LDM that transfers one register
LDM5, Strongly Ordered or Device memory Address40
LDM that transfers five registers
Strh to Strongly Ordered or Device memory Address20
Strb to Strongly Ordered or Device memory Address40
STM of seven registers
STR or STM of one register
First Wstrbm
Cache line write-back eviction
Linefills
Non-cacheable reads
15 LDR or LDM1 from Non-cacheable Normal memory Address20
14 Ldrh from Non-cacheable Normal memory Address20
Non-cacheable or write-through writes
AXI transaction splitting
20 AXI transaction splitting, data in two cache lines
Normal write merging
Example 9-1 Write merging
ARM DDI 0363E
AXI slave interface for cache RAMs
AXI slave interface
Cache parity and ECC support
TCM parity and ECC support
AXI slave control
25 AXI slave interface attributes
AXI slave characteristics
Enabling or disabling AXI slave accesses
TCM RAM access on Cache RAM access on
Accessing RAMs using the AXI slave interface
26 RAM region decode AxUSERS bit One-hot RAM select
ARADDRSMSB, see Table
TCM RAM access
27 TCM chip-select decode Btcm ports
RAM selected
Memory map when accessing the cache RAMs
Cache RAM access
This section contains the following
0010 Bank 0100 1000
Data RAM access
31 Cache data RAM bank/address decode Inputs ARADDRS1815
0001 Bank 0010 0100 1000
35 Data format, data cache, with ECC Data bit Description
34 Data format, instruction cache, with ECC
Tag RAM access
ARM DDI 0363E
43 Dirty register format, with ECC Data bit Description
Dirty RAM access
ARADDRS1815 = 4b1111
Other examples of accessing cache RAMs
About power control on Power management on
Power Control
About power control
Standby mode
Run mode
Dormant mode
Shutdown mode
Communication to the Power Management Controller
Debug state on Cache debug on
Debug
Debug host Protocol converter Debug target
Debug systems
Debug host
Protocol converter
Halting debug-mode debugging
About the debug unit
Monitor debug-mode debugging
Programming the debug unit
All other state information associated with the debug unit
Debug register interface
11.3.2 CP14 access permissions
Coprocessor registers
Coprocessor registers summary
Memory-mapped registers
Offset Register Access Mnemonic Description Hex Number
Instruction Mnemonic Description
Debug memory-mapped registers
Memory addresses for breakpoints and watchpoints
Effects of resets on debug registers
Power domains
APB port access permissions
Privilege of memory access permission
Lock
External debug interface access permissions Registers
Other Debug registers
Other registers
Debug register descriptions
Accessing debug registers
6shows the CP14 debug register map
11.4.2 CP14 c0, Debug ID Register
WRP
Debug ID Register functions
BRP
11.4.3 CP14 c0, Debug ROM Address Register
To use the Debug ID Register, read CP14 c0 with
To use the Debug ROM Address Register, read CP14 c0 with
11.4.4 CP14 c0, Debug Self Address Offset Register
Debug Self Address Offset Register functions
Debug Self Address Offset Register format
10 Debug Status and Control Register functions
11.4.5 CP14 c1, Debug Status and Control Register
Flag is set to 1 on entry to debug state
= disabled, this is the reset value
Execute ARM instruction enable bit
ARM
MOE
DTR access mode
Data Transfer Register
12 Watchpoint Fault Address Register functions
Watchpoint Fault Address Register
Vector Catch Register
Reserved RAZ
SVC
Debug State Cache Control Register
Bits Field Reset Description Value
Instruction Transfer Register
14 Debug State Cache Control Register functions
15 Debug Run Control Register functions
Debug Run Control Register
315 Reserved
Breakpoint Control Registers
Breakpoint Value Registers
17 Breakpoint Control Registers functions
Corresponding instruction address breakpoint
+0 is accessed
18 Meaning of BVR bits
BVR2220 Meaning
Watchpoint Control Registers
Watchpoint Value Registers
19 Watchpoint Value Registers functions Bits Description
20 Watchpoint Control Registers functions
11 Watchpoint Control Registers format
Operating System Lock Status Register
Accessed
21 OS Lock Status Register functions
Authentication Status Register
Device Power-down and Reset Status Register
Device Power-down and Reset Control Register
= Dbgnopwrdwn is LOW. This is the reset value
23 Prcr functions
24 Prsr functions
15 Prsr format
Processor ID Registers
Management registers
Claim Tag Set Register
Claim Registers
27 Claim Tag Set Register functions Bits Field Function
318 Reserved RAZ or Sbzp Claim tag clear Reset value is
Lock Access Register
Claim Tag Clear Register
Lock Status Register
Debug Identification Registers
Device Type Register
30 Device Type Register functions
Field Size Description
32 Fields in the Peripheral Identification Registers
33 Peripheral ID Register 0 functions
Bits Value Description
35 Peripheral ID Register 2 functions
34 Peripheral ID Register 1 functions
36 Peripheral ID Register 3 functions
37 Peripheral ID Register 4 functions
Component Identification Register
1020
1021
1022
Software debug event
Debug events
Behavior of the processor on debug events
Halting debug event
Debug event priority
Watchpoint debug events
Debug exception
Following sections describe
40shows the values in the link register after exceptions
Effect of debug exceptions on CP15 registers and Wfar
Four CP15 registers that record abort information are
Avoiding unrecoverable states
Privilege on
Debug state
Entering debug state
41 Read PC value after debug state entry
41 Read PC value after debug state entry Debug event
Behavior of the PC and Cpsr in debug state
Executing instructions in debug state
Accessing registers and memory
Writing to the Cpsr in debug state
Privilege
Effect of debug state on non-invasive debug
Coprocessor instructions
Effects of debug events on processor registers
Exceptions in debug state
Imprecise Data Abort
Precise Data abort
Imprecise Data Aborts on entry and exit from debug state
Leaving debug state
Sets the DSCR1 core restarted flag to
This section describes cache debug. It consists
Cache debug
Cache pollution in debug state
Cache coherency in debug state
Miscellaneous debug signals
APB signals
This section describes the miscellaneous debug signals
External debug interface
Changing the authentication signals
Authentication signals
42 Authentication signal restrictions Dbgen a
Non-invasive debug permitted
Issue an Instruction Synchronization Barrier ISB instruction
Example 11-1 Executing an ARM instruction through the ITR
Using the debug functionality
Debug communications channel
Rules for accessing the DCC
Debugger access to the DCC
Software access to the DCC
Example 11-5shows the code for host-to-target data transfer
Example 11-4 Target to host data transfer host end
This section describes the following operations
Programming breakpoints and watchpoints
Programming simple breakpoints and the byte address select
Example 11-6 Polling the DCC host end
Example 11-7 Setting a simple breakpoint
Setting a simple aligned watchpoint
Example 11-8 Setting a simple aligned watchpoint
Setting a simple unaligned watchpoint
45shows some examples
Example 11-9 Setting a simple unaligned watchpoint
Single-stepping
Not required
Example 11-10 Single-stepping off an instruction
Debug state entry
Example 11-11 Entering debug state
Example 11-12 Leaving debug state
Debug state exit
This section describes the following
Accessing registers and memory in debug state
Reading and writing registers through the DCC
Example 11-13 Reading an ARM register
Example 11-15shows the code to read the PC
Reading the PC in debug state
Reading the Cpsr in debug state
Example 11-16shows the code for reading the Cpsr
Reading memory
Example 11-19 Checking for an abort after memory access
Example 11-18shows the code for reading a byte of memory
Example 11-17 Writing the Cpsr
Example 11-21 Reading a word of memory
Example 11-20 Reading a block of bytes of memory
Example 11-23 Reading registers in stall mode
Example 11-22 Changing the DTR access mode
Example 11-24 Writing registers in stall mode
Fast register read/write
Example 11-25 Reading a block of words of memory
Fast memory read/write
Example 11-27 Reading a coprocessor register
Accessing coprocessor registers
11-70
Debugging systems with energy management capabilities
Emulating power down
11-72
FPU Programmer’s Model
FPU functionality
About the FPU programmer’s model
About the VFPv3-D16 architecture
FPU views of the register bank
General-purpose registers
VFPv3 architecture describes the following system registers
System registers
1shows the VFP system registers in the Cortex-R4F FPU
Fpsid is privileged access only
All hardware ID information is privileged access only
Mvfr registers are privileged access only
This is a change in VFPv3 compared to VFPv2
Fpscr Register bit functions
Floating-Point Status and Control Register, Fpscr
DNM
Rmode
LEN
Floating-Point Exception Register, Fpexc
IDE RAZ
DNM IXE RAZ UFE OFE DZE IOE IDC
Floating-Point Exception Register bit functions
Media and VFP Feature Registers, MVFR0 and MVFR1
DEX
MVFR0 Register bit functions
Full denormal arithmetic supported for VFP
MVFR1 Register bit functions
Full-compliance mode
Full-compliance mode Flush-to-zero mode Default NaN mode
Flush-to-zero mode
Default NaN mode
Complete implementation of the Ieee 754 standard
Compliance with the Ieee 754 standard
Ieee 754 standard implementation choices
NaN handling
Underflow
Comparisons
QNaN and SNaN handling
CDP
Exceptions
Integration Test Registers
About Integration Test Registers
Programming and reading Integration Test Registers
Software access using APB
Itetmif
Register Itctrl
Itmiscout
Itmiscin
1312
Processor integration testing
1110
Performing integration testing
Using the Integration Test Registers
Itetmif Register bit assignments Bits Name Function
Itetmif Register ETM interface
Itmiscin Register Miscellaneous Inputs
Itmiscout Register Miscellaneous Outputs
Itmiscout Register bit assignments Bits Name Function
Bits Name Function
Integration Mode Control Register Itctrl
Dbgrestart
Etmextout
7shows the fields of the Itctrl Register
Bits Access Reset value Name Function
RAZ/SBZP
Intmode
Multiplies on Divide on Branches on
Cycle Timings and Interlock Behavior
Dual issue on
Instruction execution overview
About cycle timings and interlock behavior
Flag-setting instructions
Following sequence where R1 is a Late Reg takes two cycles
Conditional instructions
Definition of terms
Assembler language syntax
Instruction Behavior Sequence
Register interlock examples
Takes two cycles because there are no register dependencies
Takes three cycles because of the result latency of R1
Cycle counts if destination is not PC
Data processing instructions
Cycle counts if destination is the PC
Shifter
Example interlocks
Register controlled shifts
QADD, QDADD, QSUB, and Qdsub instructions
SEL
Media data-processing
Instruction sequence Behavior
Sum of Absolute Differences SAD
Result of the USAD8 instruction
USAD8 instruction
Umlals
Multiplies
14-13
Divide
10 Branch instruction cycle timing behavior
Branches
Example instruction Cycles Memory Comments
Processor state updating instructions
Mode changing
All MRS instructions
All MSR instructions to the Spsr
13shows the cycle timing behavior for loads to the PC
Single load and store instructions
13 Cycle timing behavior for loads to the PC
Base register update
Example instruction Cycles Memory Result Comments Latency
14-19
Load and Store Double instructions
Register offset, then 3-issue cycles
Write-back
Load and Store Multiple instructions
Correct condition prediction and correct
Load Multiples, where the PC is in the register list
Return stack prediction
Correct condition prediction and incorrect
14-23
RFE and SRS instructions
Clrex
Synchronization instructions
Some instructions such as cache operations take more cycles
Coprocessor instructions
Prefetch Abort Undefined Instruction
SVC formerly SWI
Miscellaneous instructions
Blocking and serializing
Floating-point register transfer instructions
Serializing
Bit aligned address
Floating-point load/store instructions
Not aligned
2,2
4,5
2,3
Floating-point single-precision data processing instructions
Floating-point double-precision data processing instructions
Dual issue rules Permitted combinations on
Dual issue
Dual issue rules
Permitted combinations
Dual issue First instruction Second instruction Case
28 Permitted instruction combinations
Any single-precision CDPi, excluding
Case F2stb
Multiply-accumulate instructionso
Case F2Db
Processor timing on Processor timing parameters on
AC Characteristics
Processor timing
Input port timing parameters
Processor timing parameters
Clock uncertainty 10%
Clock uncertainty 50%
4shows the input timing parameters for the AXI master port
3shows the timing parameters for the interrupt input ports
Clock uncertainty 60%
Rreadys
5shows the input timing parameters for the AXI slave port
7shows the input timing parameters for the ETM input ports
6shows the input timing parameters for the debug input ports
Clock uncertainty 65%
8shows the timing parameters for the test input ports
Clock uncertainty 40%
11shows the timing parameters for the interrupt output ports
Output ports timing parameters
Write response channel Clock uncertainty 60%
13shows the timing parameters for the AXI slave output ports
BRESPS10
Clock uncertainty 45%
16shows the timing parameters for the test output ports
Fpidc
18shows the timing parameters for the FPU output signals
15-13
FPU signals on page A-23
Processor Signal Descriptions
Any
About the processor signal descriptions
From any clock
Table A-1 Global signals
Global signals
Signal Direction Clocking Description
Table A-2shows the processor configuration signals
Configuration signals
Table A-2 Configuration signals
Information
Tie High for odd parity
Tie LOW for even parity
RMWENRAM10b
Interrupt signals, including VIC interface signals
Table A-4 AXI master port signals for the L2 interface
L2 interface signals
AXI master port
Identification tag for the write response signal
Identification tag for the write data group of signals
Identification tag for the read address group of signals
Protection signals provide addition information about a bus
Table A-5 AXI master port error detection signals
AXI master port error detection signals
Table A-6 AXI slave port signals for the L2 interface
AXI slave port
AXI specification
Protection information, privileged/normal access. AWPROT0
Protection information, privileged/normal access. ARPROT0
One to 16. a four bit binary value minus one determines
ATCM, one hot. AWUSERS30 signal is not part
AXI slave port error detection signals
Standard AXI specification
Table A-7 AXI slave port error detection signals
Table A-8shows the Atcm port signals
TCM interface signals
Table A-9shows the B0TCM port signals
Table A-10 B1TCM port signals
Table A-10shows the B1TCM port signals
= DMA
Address for B1TCM data RAM
B1TCM RAM access is sequential
Write data for B1TCM data RAM
Write parity or ECC code for B1TCM
Table A-11shows the dual redundant core interface signals
Dual core interface signals
Table A-11 Dual core interface signals
Table A-13shows the debug miscellaneous signals
Debug interface signals
Table A-12 Debug interface signals
Input Tie-off Debug ROM physical address valid
Table A-13 Debug miscellaneous signals
Input Tie-off Debug self-address offset
Input Tie-off Debug self-address offset valid
Table A-14shows the ETM interface signals
ETM interface signals
Table A-14 ETM interface signals
Table A-15shows the test signals
Test signals
Table A-15 Test signals
Table A-16shows the Mbist signals
Mbist signals
Table A-17shows the validation signals
Validation signals
Table A-18 FPU signals
FPU signals
ECC scheme selection guidelines on page B-2
ECC Schemes
ECC scheme selection guidelines
Revisions
NCPUHALT removed from timing diagram Added sections
Clarified byte-invariant big-endian format
Clarified little-endian format
Change Location
Table C-1 Differences between issue B and issue C
No technical changes
Table C-2 Differences between issue C and issue D
Abort, and an internal or External Abort
Glossary
See also Data Abort, External Abort and Prefetch Abort
Base register write-back
See Advanced High-performance Bus
See also Advanced High-performance Bus
That are divisible by four and two respectively
See Advanced Microcontroller Bus Architecture
Active transfer
Active read transaction
Active write transaction
Completed transfer
Read issuing capability
Read ID width
Write ID capability
Write ID width
See also Beat
See also Burst
Accessed in parallel during a cache look-up
Accesses are expected to be word-aligned
See also Word-invariant
Bus
See also Dirty
See also Clean
See Embedded Trace Macrocell
By individual implementations
An instruction that is architecturally Undefined
Option chosen does not affect software compatibility
Precision and the fraction is all zeros
See also Halt mode
Serviced while normal program execution is suspended
See Cold reset
Result of attempting to access invalid instruction memory
See Should Be One
Or equal to 1 and is not restricted to being a power of two
See Should Be Zero
See Boundary scan chain
Increment of +2
See Debug test access port
Destination precision
User trap handler is executed
Bit for the exception is set
Expected behavior for an unaligned access
Processor-specific. a victim is also known as a cast out
A processor
Cache terminology diagram
