ARM r1p3, R4, R4F

Introduction

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Table1-2 describes the various features that can be pin-configured to be either enabled or disabled at reset. It also shows which CP15 register field provides software configuration of the feature when the processor is out of reset. All of these fields exist in either the system control register, or one of the auxiliary control registers.

BTCM at reset Disabled - Pin

EnabledbBase address configured

Base address

0x0

Pin and build

Peripheral ID

RevAnd field

Any 4-bit value - Build

AXI slave

interface

No AXI-slave - Build

AXI-slave included -

TCM Hard Error

Cache

No TCM Hard Error Cache - Build

TCM Hard Error Cache

included c

Non-Maskable

FIQ Interrupt

Disabled (FIQ can be

masked by software

-Pin

Enabled -

Parity typedOdd parity - Pin

Even parity -

a. Only available with the Cortex-R4F processor.

b. Only if the relevant TCM port(s) are included.

c. Only if at least one TCM port is included and uses ECC error checking.

d. Only relevant if at least one TCM port is included and uses parity error checking, one of the caches includes parity checking,

or AXI or TCM bus parity is included.

Table1-1 Configurable options (continued)

Feature Options Sub-options Build-configuration

or pin-configuration

Table1-2 Configurable options at reset

Feature Options Register

Exception endianness Little-endian/big-endian data for exception handling EE

Exception state ARM/Thumb state for exception handling TE

Exception vector table Base address for exception vectors:

0x00000000

0xFFFF0000

TCM error checking ATCM parity check enableaATCMP C E N

BTCM parity check enable, for B0TCM and B1TCM independently aB0TCMPCEN/

B1TCMPCEN

ATCM ECC check enableaATCMP C E N

BTCM ECC check enabled, for B0TCM and B1TCM togetheraB0TCMPCEN/

B1TCMPCEN