ARM R4F Configurable options at reset Feature Options Register, Atcmpcen, B0TCMPCEN, B1TCMPCEN

Introduction

Table 1-1 Configurable options (continued)

Feature	Options	Sub-options	Build-configuration
			or pin-configuration
BTCM at reset	Disabled	-	Pin
	Enabledb	Base address configured	Pin and build
		Base address 0x0
Peripheral ID	Any 4-bit value	-	Build
RevAnd field
AXI slave	No AXI-slave	-	Build
interface
	AXI-slave included	-
TCM Hard Error	No TCM Hard Error Cache	-	Build
Cache
	TCM Hard Error Cache	-
	included c
Non-Maskable	Disabled (FIQ can be	-	Pin
FIQ Interrupt	masked by software
	Enabled	-
Parity typed	Odd parity	-	Pin
	Even parity	-

a.Only available with the Cortex-R4F processor.

b.Only if the relevant TCM port(s) are included.

c.Only if at least one TCM port is included and uses ECC error checking.

d.Only relevant if at least one TCM port is included and uses parity error checking, one of the caches includes parity checking, or AXI or TCM bus parity is included.

Table 1-2describes the various features that can be pin-configured to be either enabled or disabled at reset. It also shows which CP15 register field provides software configuration of the feature when the processor is out of reset. All of these fields exist in either the system control register, or one of the auxiliary control registers.

Table 1-2 Configurable options at reset

Feature	Options	Register
Exception endianness	Little-endian/big-endian data for exception handling	EE
Exception state	ARM/Thumb state for exception handling	TE
Exception vector table	Base address for exception vectors: 0x00000000/0xFFFF0000	V
TCM error checking	ATCM parity check enablea	ATCMPCEN
	BTCM parity check enable, for B0TCM and B1TCM independently a	B0TCMPCEN/
		B1TCMPCEN
	ATCM ECC check enablea	ATCMPCEN
	BTCM ECC check enabled, for B0TCM and B1TCM togethera	B0TCMPCEN/
		B1TCMPCEN

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