ARM R4F, r1p3 Identifiers for AXI bus accesses, Outstanding write/read access on different IDs

Level Two Interface

9.2.1Identifiers for AXI bus accesses

Accesses on the AXI bus use ID values as follows:

Outstanding write/read access on different IDs

This means, for example, that a Non-cacheable(NC) read and linefills can be outstanding on the AXI bus simultaneously as long as the IDs are different.

At the same time, there can be:

•up to seven outstanding reads, each with one of seven different ID values, that consists of:

—a data side read NC access, RID0

—an instruction side read NC access or an instruction side read Cacheable access, RID1

—five outstanding data side linefills on the AXI bus, RID3 - RID7.

•up to two IDs on outstanding writes, that consist of:

—single or burst NC writes or write-through(WT) writes, WID0

—evictions, WID1.

Outstanding write accesses with the same ID

When the address and data of the first write are both put on AXI bus, another write request with same ID can be sent when the address or data channel is released. For example, the new address can be sent with the same ID, before the target accepts the data of the first write.

Note

•The AXI master does not generate two outstanding read accesses with the same ID.

•The AXI master does not interleave write data from two different bursts, even if the bursts have different IDs.

9.2.2Write response

The AXI master requires that the slave does not return a write response until it has received both the write data and the write address.

9.2.3Linefill buffers and the AXI master interface

On the data side there are two LineFill Buffers (LFBs), LFB0 and LFB1. Each request from the data cache controller or from the STore Buffer (STB) can be allocated to either LFB0 or LFB1.

On the instruction side, there is one LFB. This is the Instruction LFB (ILFB), that treats instruction linefill requests or Non-cacheable instruction reads in the same way.

The linefill buffers:

•get returned data from the AXI bus for linefill requests

•get returned data from the AXI bus for any Non-cacheable LDR or LDMs

•get data from the STB to write as a burst on the AXI bus (LFB0 and LFB1 only).

Single writes do not use LFBs.

The LFBs are 256 bits wide so that an entire cache line can be written to the cache RAMs in one cycle. While the LFB is being filled from L2 memory, its bytes can be merged with write data from the STB.

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