ARM r1p3, R4, R4F List of Tables Cortex-R4 and Cortex-R4F Technical Reference

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List of TablesCortex-R4 and Cortex-R4F Technical Reference

Manual

Change History ............................................................................................................................... ii

Table1 -1 Configurable options ................................................................................................................. 1-13

Table 1-2 Configurable options at reset .................................................................................................... 1-15

Table 1-3 ID values for different product versions .................................................................................... 1-25

Table2-1 Register mode identifiers ............................................................................................................ 2-8

Table2-2 GE[3:0] settings ........................................................................................................................ 2-12

Table2 -3 PSR mode bit values ................................................................................................................ 2-14

Table2 -4 Exception entry and exit ............................................................................................................ 2-16

Table 2-5 Configuration of exception vector address locations ................................................................ 2-26

Table2-6 Exception vectors ...................................................................................................................... 2-26

Table 2-7 Jazelle register instruction summary ......................................................................................... 2-27

Table 3-1 Reset modes ............................................................................................................................... 3-7

Table 4-1 System control coprocessor register functions ........................................................................... 4-3

Table 4-2 Summary of CP15 registers and operations ............................................................................... 4-9

Table4 -3 Main ID Register bit functions ................................................................................................... 4-15

Table4 -4 Cache Type Register bit functions ............................................................................................ 4-16

Table4 -5 TCM Type Register bit functions ............................................................................................... 4-16

Table4 -6 MPU Type Register bit functions .............................................................................................. 4-17

Table 4-7 Processor Feature Register 0 bit functions ............................................................................... 4-19

Table 4-8 Processor Feature Register 1 bit functions ............................................................................... 4-19

Table 4-9 Debug Feature Register 0 bit functions .................................................................................... 4-20

Table 4-10 Memory Model Feature Register 0 bit functions ....................................................................... 4-22

Table 4-11 Memory Model Feature Register 1 bit functions ....................................................................... 4-23

Table 4-12 Memory Model Feature Register 2 bit functions ....................................................................... 4-24

Table 4-13 Memory Model Feature Register 3 bit functions ....................................................................... 4-25

Table 4-14 Instruction Set Attributes Register 0 bit functions ..................................................................... 4-26

Table 4-15 Instruction Set Attributes Register 1 bit functions ..................................................................... 4-28