ARM r1p3, R4, R4F

Level Two Interface

ID013010 Non-Confidential, Unrestricted Access

9.3.3 Linefills

Loads and instruction fetches from Normal, Cacheable memory that do not hit in the cache

generate a cache linefill when the appropriate cache is enabled. Table9-12 shows the values of

ARADDRM, ARBURSTM, ARSIZEM, and ARLENM for cache linefills.

9.3.4 Cache line write-back (eviction)

When a valid and dirty cache line is evicted from the d-cache, a write-back of the data must

occur. Table9-13 shows the values of AWADDRM, AWBURSTM, AWSIZ E M , and

AWLENM for cache line write-backs, over the AXI master interface.

9.3.5 Non-cacheable reads

Load instructions accessing Non-cacheable Normal memory generate AXI bursts that are not

necessarily the same size or length as the instruction implies. In addition, if the data to be read

is contained in the store buffer, the instruction might not generate an AXI read transaction at all.

The tables in this section give examples of the types of AXI transaction that might result from

various load instructions, accessing various addresses in Non-cacheable Normal memory. They

are provided as examples only, and are not an exhaustive description of the AXI transactions.

Depending on the state of the processor, and the timing of the accesses, the actual bursts

generated might have a different size and length to the examples shown, even for the same

instruction.

Table9-14 shows possible values of ARADDRM, ARBURSTM, ARSIZEM, and ARLENM

for an

LDRH

from bytes 0-7 in Non-cacheable Normal memory.

Table9-12 Linefill behavior on the AXI interface

Address[4:0]a

a. These are the bottom five bits of the address of the access that cause the linefill, that

is, the address of the critical word.

ARADDRM ARBURSTM ARSIZEM ARLENM

0x00

0x07 0x00

Wrap 64-bit 4 data transfers

0x08

0x0F 0x08

Wrap 64-bit 4 data transfers

0x10

0x17 0x10

Wrap 64-bit 4 data transfers

0x18

0x1F 0x18

Wrap 64-bit 4 data transfers

Table9-13 Cache line write-back

AWADDRM[4:0] AWBURSTM AWSIZEM AWLENM

0x00

Incr 64-bit 4 data transfers

Table9-14 LDRH from Non-cacheable Normal memory

Address[2:0] ARADDRM ARBURSTM ARSIZEM ARLENM

0x0

(byte 0)

0x00

Incr 16-bit 1 data transfer

0x1

(byte 1)

0x00

Incr 32-bit 1 data transfer

0x2

(byte 2)

0x00

Incr 64-bit 1 data transfer

0x3

(byte 3)

0x03

Incr 32-bit 2 data transfers