Programmer’s Model

Note

If the EmbeddedICE-RT logic is configured into Halt debug-mode, a breakpoint instruction causes the processor to enter debug state. See Halting debug-mode debugging on page 11-3.

2.8.8Exception vectors

You can configure the location of the exception vector addresses by setting the V bit in CP15 c1 System Control Register to enable HIVECS, as Table 2-5shows.

Table 2-5 Configuration of exception vector address locations

Value of V bit

Exception vector

base location

 

 

 

0

0x00000000

 

 

1 (HIVECS)

0xFFFF0000

 

 

Table 2-6shows the exception vector addresses and entry conditions for the different exception types.

Table 2-6 Exception vectors

Exception

Offset from

Mode on entry

A bit on entry

F bit on entry

I bit on entry

vector base

 

 

 

 

 

 

 

 

 

 

 

Reset

0x00

Supervisor

Set

Set

Set

 

 

 

 

 

 

Undefined instruction

0x04

Undefined

Unchanged

Unchanged

Set

 

 

 

 

 

 

Software interrupt

0x08

Supervisor

Unchanged

Unchanged

Set

 

 

 

 

 

 

Abort (prefetch)

0x0C

Abort

Set

Unchanged

Set

 

 

 

 

 

 

Abort (data)

0x10

Abort

Set

Unchanged

Set

 

 

 

 

 

 

IRQ

0x18

IRQ

Set

Unchanged

Set

 

 

 

 

 

 

FIQ

0x1C

FIQ

Set

Set

Set

 

 

 

 

 

 

ARM DDI 0363E

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ARM R4F, r1p3 manual Exception vectors