ARM R4F, r1p3 manual Vector Catch Register format 11-20

		List of Figures
Figure 11-3	Debug ROM Address Register format	11-12
Figure 11-4	Debug Self Address Offset Register format	11-13
Figure 11-5	Debug Status and Control Register format	11-14
Figure 11-6	Watchpoint Fault Address Register format	11-19
Figure 11-7	Vector Catch Register format	11-20
Figure 11-8	Debug State Cache Control Register format	11-21
Figure 11-9	Debug Run Control Register format	11-22
Figure 11-10	Breakpoint Control Registers format	11-23
Figure 11-11	Watchpoint Control Registers format	11-27
Figure 11-12	OS Lock Status Register format	11-29
Figure 11-13	Authentication Status Register format	11-29
Figure 11-14	PRCR format	11-30
Figure 11-15	PRSR format	11-31
Figure 11-16	Claim Tag Set Register format	11-33
Figure 11-17	Claim Tag Clear Register format	11-34
Figure 11-18	Lock Status Register format	11-34
Figure 11-19	Device Type Register format	11-35
Figure 12-1	FPU register bank	12-3
Figure 12-2	Floating-Point System ID Register format	12-5
Figure 12-3	Floating-Point Status and Control Register format	12-6
Figure 12-4	Floating-Point Exception Register format	12-7
Figure 12-5	MVFR0 Register format	12-8
Figure 12-6	MVFR1 Register format	12-9
Figure 13-1	ITETMIF Register bit assignments	13-7
Figure 13-2	ITMISCOUT Register bit assignments	13-8
Figure 13-3	ITMISCIN Register bit assignments	13-9
Figure 13-4	ITCTRL Register bit assignments	13-9

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