ARM r1p3, R4F manual About the TCMs, TCM attributes and permissions

Level One Memory System

8.4About the TCMs

The processor has two TCM interfaces to support the connection of local memories. The ATCM interface has one TCM port. The BTCM interface can support one or two TCM ports. Each TCM port is a physical connection on the processor that is suitable for connection to SRAM with minimal glue logic. These ports are optimized for low latency memory.

The TCM ports are designed to be connected to RAM, or RAM-like memory, that is, Normal-type memory. The processor can issue speculative read accesses on these interfaces, and interrupt store instructions that have issued some but not all of their write accesses. Therefore, both read and write accesses through the TCM interfaces can be repeated. This means that the TCM ports are generally not suitable for read- or write-sensitive devices such as FIFOs. ROM can be connected to the TCM ports, but normally only if ECC is not used. See Hard errors on page 8-5.If the access is speculative, the processor ignores any error or retry signaled on the TCM port.

The TCM ports also have wait and error signals to support slow memories and external error detection and correction. For more information, see External TCM errors on page 8-16.

The PFU can read data using the TCM interfaces. The LSU and AXI slave can each read and write data using the TCM interfaces.

Each TCM interface has a dedicated base address that you can place anywhere in the physical address map, and must not be backed by memory implemented externally. The ATCM and BTCM interfaces must have separate base addresses and must not overlap.

This section describes:

•TCM attributes and permissions

•ATCM and BTCM configuration on page 8-14

•TCM internal error detection and correction on page 8-14

•TCM arbitration on page 8-15

•TCM initialization on page 8-16

•TCM port protocol on page 8-16

•External TCM errors on page 8-16

•AXI slave interfaces for TCMs on page 8-17.

8.4.1TCM attributes and permissions

Accesses to the TCMs from the LSU and PFU are checked against the MPU for access permission. Memory access attributes and permissions are not exported on this interface. Reads that generate an MPU fault are broadcast on the TCM interface but the abort is taken before the data is used, ensuring protection is maintained.

TCMs always behave as Non-cacheable Non-shared Normal memory, irrespective of the memory type attributes defined in the MPU for a memory region containing addresses held in the TCM. Access permissions for TCM accesses are the same as the permission attributes that the MPU assigns to the same address. See Chapter 7 Memory Protection Unit for more information about memory attributes, types, and permissions.

Note

Any address in an MPU region with device or strongly-ordered memory type attributes is implicitly given execute-never(XN) permissions. If such an address is also in a TCM region, XN permissions are applied to TCM accesses to that address. None of the other device or strongly-ordered behaviors apply to an address in a TCM region.

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