ARM r1p3, R4F manual Adfsr and Aifsr bit functions

		List of Tables
Table 4-16	Instruction Set Attributes Register 2 bit functions	4-29
Table 4-17	Instruction Set Attributes Register 3 bit functions	4-30
Table 4-18	Instruction Set Attributes Register 4 bit functions	4-31
Table 4-19	Current Cache Size Identification Register bit functions	4-33
Table 4-20	Bit field and register encodings for Current Cache Size Identification Register	4-33
Table 4-21	Current Cache Level ID Register bit functions	4-34
Table 4-22	Cache Size Selection Register bit functions	4-35
Table 4-23	System Control Register bit functions	4-36
Table 4-24	Auxiliary Control Register bit functions	4-38
Table 4-25	Secondary Auxiliary Control Register bit functions	4-42
Table 4-26	Coprocessor Access Register bit functions	4-45
Table 4-27	Fault Status Register encodings	4-45
Table 4-28	Data Fault Status Register bit functions	4-46
Table 4-29	Instruction Fault Status Register bit functions	4-47
Table 4-30	ADFSR and AIFSR bit functions	4-48
Table 4-31	MPU Region Base Address Registers bit functions	4-50
Table 4-32	Region Size Register bit functions	4-51
Table 4-33	MPU Region Access Control Register bit functions	4-52
Table 4-34	Access data permission bit encoding	4-52
Table 4-35	MPU Memory Region Number Register bit functions	4-53
Table 4-36	Functional bits of c7 for Set and Way	4-56
Table 4-37	Widths of the set field for L1 cache sizes	4-56
Table 4-38	Functional bits of c7 for address format	4-57
Table 4-39	BTCM Region Register bit functions	4-58
Table 4-40	ATCM Region Register bit functions	4-59
Table 4-41	Slave Port Control Register bit functions	4-60
Table 4-42	nVAL IRQ Enable Set Register bit functions	4-62
Table 4-43	nVAL FIQ Enable Set Register bit functions	4-63
Table 4-44	nVAL Reset Enable Set Register bit functions	4-64
Table 4-45	nVAL Debug Request Enable Set Register bit functions	4-65
Table 4-46	nVAL IRQ Enable Clear Register bit functions	4-66
Table 4-47	nVAL FIQ Enable Clear Register bit functions	. 4-67
Table 4-48	nVAL Reset Enable Clear Register bit functions	4-67
Table 4-49	nVAL Debug Request Enable Clear Register bit functions	4-68
Table 4-50	nVAL Cache Size Override Register	4-69
Table 4-51	nVAL instruction and data cache size encodings	4-69
Table 4-52	Correctable Fault Location Register - cache	4-71
Table 4-53	Correctable Fault Location Register - TCM	4-71
Table 4-54	Build Options 1 Register	4-72
Table 4-55	Build Options 2 Register	4-73
Table 6-1	Event bus interface bit functions	6-2
Table 6-2	PMNC Register bit functions	6-7
Table 6-3	CNTENS Register bit functions	6-9
Table 6-4	CNTENC Register bit functions	6-10
Table 6-5	Overflow Flag Status Register bit functions	6-11
Table 6-6	SWINCR Register bit functions	6-12
Table 6-7	Performance Counter Selection Register bit functions	6-13
Table 6-8	EVTSELx Register bit functions	6-14
Table 6-9	USEREN Register bit functions	6-15
Table 6-10	INTENS Register bit functions	6-16
Table 6-11	INTENC Register bit functions	6-17
Table 7-1	Default memory map	7-2
Table 7-2	Memory attributes summary	7-7
Table 7-3	TEX[2:0], C, and B encodings	7-9
Table 7-4	Inner and Outer cache policy encoding	7-10
Table 8-1	Types of aborts	8-11
Table 8-2	Cache parity error behavior	8-21
Table 8-3	Cache ECC error behavior	8-22
Table 8-4	Tag RAM bit descriptions, with parity	8-26
Table 8-5	Tag RAM bit descriptions, with ECC	8-26

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