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ARM r1p3 manual Cortex-R4 and Cortex-R4F Technical Reference Manual, Chapter Introduction

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Contents

Cortex-R4 and Cortex-R4F Technical Reference Manual

Preface

		About this book	xvii
		Feedback	xxi
Chapter 1	Introduction
	1.1	About the processor	1-2
	1.2	About the architecture	1-3
	1.3	Components of the processor	1-4
	1.4	External interfaces of the processor	1-11
	1.5	Power management	1-12
	1.6	Configurable options	1-13
	1.7	Execution pipeline stages	1-17
	1.8	Redundant core comparison	1-19
	1.9	Test features	1-20
	1.10	Product documentation, design flow, and architecture	1-21
	1.11	Product revision information	1-24
Chapter 2	Programmer’s Model
	2.1	About the programmer’s model	2-2
	2.2	Instruction set states	2-3
	2.3	Operating modes	2-4
	2.4	Data types	2-5
	2.5	Memory formats	2-6
	2.6	Registers	2-7
	2.7	Program status registers	2-10
	2.8	Exceptions	2-16
	2.9	Acceleration of execution environments	2-27

ARM DDI 0363E	Copyright © 2009 ARM Limited. All rights reserved.	iii
ID013010	Non-Confidential, Unrestricted Access

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ARM r1p3 manual Cortex-R4 and Cortex-R4F Technical Reference Manual, Chapter Introduction

Contents

Cortex-R4 and Cortex-R4F Cortex-R4 and Cortex-R4F Technical Reference ManualCopyright 2009 ARM Limited. All rights reserved Chapter Introduction Cortex-R4 and Cortex-R4F Technical Reference ManualChapter Processor Initialization, Resets, and Clocking Chapter AC Characteristics Appendix B ECC Schemes List of Tables Adfsr and Aifsr bit functions Dirty register format, with ECC 11-12 Example interlocks 14-11 Table A-18 FPU signals Table C-1 List of Figures Cache operations C7 format for Set and Way Vector Catch Register format 11-20 Feedback on PrefaceIdentifies the major revision of the product Using this bookAbout this book Product revision statusTypographical ConventionsSignals Timing diagramsOther publications Further readingThis section lists publications by ARM and by third parties ARM publicationsFeedback on this book FeedbackARM welcomes feedback on this product and its documentation Feedback on this productIntroduction About the processor About the architecture System control coprocessor on Interrupt handling on Components of the processorThis section describes the main components of the processor Debug onPrefetch unit Data Processing UnitFloating Point Unit Load/store unitInstruction and data caches Memory Protection UnitTCM interfaces AXI slave interface Error correction and detection5 L2 AXI interfaces AXI master interfaceReal-time debug facilities DebugSystem performance monitoring ETM interfaceLow interrupt latency System control coprocessorInterrupt handling VIC portChanges Return from exception using data from the stackAPB Debug interface Processor has the following interfaces for external accessExternal interfaces of the processor APB Debug interface ETM interface Test interfaceShutdown mode Power managementRun mode Standby modeConfigurable options Configurable optionsAtcm MPU BtcmVFP FPU includedaB1TCMPCEN Configurable options at reset Feature Options RegisterAtcmpcen B0TCMPCENAtcmrmw AtcmecenB0TCMECEN B1TCMECENExecution pipeline stages Names of the pipeline stages and their functions areInstruction decode Write-back of data from the execution pipelines First stage of data memory accessIss Execute stagesRedundant core comparison Test features Product documentation, design flow, and architecture DocumentationDesign flow Architectural information Build configurationConfiguration inputs Software configurationAdvanced Microcontroller Bus Architecture protocol Processor identification Product revision informationRevision field, Debug ID Register Variant field, Main ID RegisterRevision field, Main ID Register Variant field, Debug ID RegisterExceptions on Programmer’s ModelRegisters on Program status registers onAbout the programmer’s model Thumb state Switching stateInstruction set states ARM stateOperating modes Data types Little-endian format Memory formatsByte-invariantbig-endian format Little-endian format Byte-invariant big-endian formatRegister set RegistersRegister mode identifiers Mode Mode identifier General registers and program counter N, Z, C, and V bits Program status registersIT bits Q bitJ bit DNM bitsGE bits Non-maskable fast interrupts on E bitA bit I and F bitsModification of PSR bits by MSR instructions PSR mode bit valuesM40 Mode Visible state registers Thumb M bitsARM DDI 0363E Exception entry and exit summary Reset on Interrupts on Aborts onExceptions Exception entry and exit summaryLeaving an exception Taking an exceptionReset InterruptsInterrupt request Fast interrupt request Program status registers on Non-maskable fast interruptsNon-maskable fast interrupts Interrupt controller Interrupt entry flowchartInterrupt entry sequence Precise aborts AbortsPrefetch aborts Data abortsAborts in Strongly Ordered and Device memory Imprecise abortsSupervisor call instruction Abort handlerBreakpoint instruction Undefined instructionException vectors Acceleration of execution environments Architecture Reference Manual Unaligned and mixed-endian data access supportBig-endian instruction support Initialization on Processor Initialization, Resets, and ClockingResets on Reset modes on2 CRS InitializationCaches on TCM on 1 MPUCaches 5 TCMPreloading TCMs DMA into TCM Write to TCM directly from debuggerPreloading TCMs with parity or ECC Using TCMs from reset NSYSPORESET ResetsNRESET PRESETDBGnPower-on reset Reset modesProcessor reset Normal operationHalt operation Clock gating ClockingAXI interface clocking Clock gating AXI interface clockingSystem Control Coprocessor System control coprocessor functional groups About the system control coprocessorSystem control coprocessor register functions Function Register/operation Reference to descriptionFcse PID System performance Performance monitoring System control and configurationConfiguration Region TCM control TCM StatusCache control and configuration MPU control and configurationSystem performance monitor TCM control and configurationSystem performance monitor registers System validationARM DDI 0363E System control coprocessor registers Register allocationRAZ Number Enable Undefined MPU Region Access Read/writeUndefined MPU Region Size Read/write Control Undefined MPU Memory Region Read/writeARM DDI 0363E Undefined C3-c11 C12 Performance Monitor Read/write Event Select Read/write Unpredictable Performance MonitorCount Undefined Writes Context ID Read/write C14 User Enable Read/writeUndefined C1-c15 C12 C0-c15 C13 RAZ,ignore7shows the arrangement of bits in the register 2 c0, Main ID Register3 c0, Cache Type Register Main ID Register bit functionsBits Field Function TCM Type Register bit functions Bits Field Function To access the Cache Type Register, read CP15 with4 c0, TCM Type Register Cache Type Register bit functions Bits Field FunctionTCM Type Register bit functions To access the TCM Type Register, read CP15 withTo access the MPU Type Register, read CP15 with 5 c0, MPU Type RegisterProcessor Feature Registers C0, Processor Feature Register 0, PFR06 c0, Multiprocessor ID Register Processor Feature Register 1 bit functions To access the Processor Feature Register 0 read CP15 withC0, Processor Feature Register 1, PFR1 Processor Feature Register 0 bit functions3124 Reserved To access the Processor Feature Register 1 read CP15 with8 c0, Debug Feature Register Debug Feature Register 0 bit functionsC0, Memory Model Feature Register 0, MMFR0 To access the Debug Feature Register 0 read CP15 with9 c0, Auxiliary Feature Register Memory Model Feature Registers10 Memory Model Feature Register 0 bit functions C0, Memory Model Feature Register 1, MMFR111 Memory Model Feature Register 1 bit functions 16 Memory Model Feature Register 1 formatC0, Memory Model Feature Register 2, MMFR2 WFIDMB C0, Memory Model Feature Register 3, MMFR3 13 Memory Model Feature Register 3 bit functions3112 Reserved Instruction Set Attributes Registers C0, Instruction Set Attributes Register 0, ISAR014 Instruction Set Attributes Register 0 bit functions 20 Instruction Set Attributes Register 1 format C0, Instruction Set Attributes Register 1, ISAR1C0, Instruction Set Attributes Register 2, ISAR2 ITEIndicates support for if then instructions 16 Instruction Set Attributes Register 2 bit functions PSRIndicates support for PSR instructions C0, Instruction Set Attributes Register 3, ISAR3 17 Instruction Set Attributes Register 3 bit functionsThumb instruction sets 23 Instruction Set Attributes Register 4 format C0, Instruction Set Attributes Register 4, ISAR4C0, Instruction Set Attributes Registers 12 c0, Current Cache Size Identification Register18 Instruction Set Attributes Register 4 bit functions 8KB 4KB3130 Reserved 13 c0, Current Cache Level ID Register15 c1, System Control Register 14 c0, Cache Size Selection RegisterNmfi 23 System Control Register bit functionsAFE TRE= strict alignment fault checking enabled Enables L1 data cache= data caching disabled. This is the reset value = data caching enabledAuxiliary Control Registers C1, Auxiliary Control Register24 Auxiliary Control Register bit functions Deolp AxiscenAxiscuen DilsmDnch RsdisDbwr DlfoC15, Secondary Auxiliary Control Register 25 Secondary Auxiliary Control Register bit functions UFC DoofmacsIXC OFCAtcmecc 17 c1, Coprocessor Access RegisterPrimary input RMWENRAM1 defines the reset value Primary input RMWENRAM0 defines the reset valueFault Status and Address Registers C5, Data Fault Status RegisterAll other encodings for these FSR bits are Reserved C5, Instruction Fault Status Register 28 Data Fault Status Register bit functionsTo use the Dfsr read or write CP15 with 29 Instruction Fault Status Register bit functions To access the Ifsr read or write CP15 withC5, Auxiliary Fault Status Registers There are two auxiliary fault status registers= Btcm C6, Data Fault Address Register30 Adfsr and Aifsr bit functions = Atcm19 c6, MPU memory region programming registers C6, Instruction Fault Address RegisterC6, MPU Region Base Address Registers C6, MPU Region Size and Enable RegistersC6, MPU Region Access Control Registers 158 Sub-region disable32 Region Size Register bit functions TEX 33 MPU Region Access Control Register bit functions35 MPU Memory Region Number Register bit functions 34 Access data permission bit encodingC6, MPU Memory Region Number Register UNPCache operations Point of Coherency PoCPoint of Unification PoU Set and Way format Invalidate and clean operations37 Widths of the set field for L1 cache sizes Size Set 37shows the cache sizes and the resultant bit range for SetAddress format 36 Functional bits of c7 for Set and Way38 Functional bits of c7 for address format Bits Field Data Synchronization Barrier operationData Memory Barrier operation 21 c9, Btcm Region RegisterTo access the Btcm Region Register, read or write CP15 with 22 c9, Atcm Region Register39 Btcm Region Register bit functions 40 Atcm Region Register bit functions To access the Atcm Region Register, read or write CP15 with23 c9, TCM Selection Register 24 c11, Slave Port Control RegisterRAZ/UNP 25 c13, Fcse PID Register26 c13, Context ID Register 312 Reserved27 c13, Thread and Process ID Registers C15, nVAL IRQ Enable Set Register Validation RegistersCcnt overflow IRQ request Ccnt overflow FIQ request C15, nVAL FIQ Enable Set RegisterC15, nVAL Reset Enable Set Register C15, nVAL Debug Request Enable Set RegisterCcnt overflow reset request Ccnt overflow debug request C15, nVAL IRQ Enable Clear Register48 nVAL IRQ Enable Clear Register format C15, nVAL FIQ Enable Clear Register303 Reserved UNP or Sbzp C15, nVAL Reset Enable Clear Register51 nVAL Debug Request Enable Clear Register format C15, nVAL Debug Request Enable Clear RegisterB0000 4kB B0001 8kB B0011 16kB B0111 32kB B1111 64kB C15, nVAL Cache Size Override Register50 nVAL Cache Size Override Register 318 Reserved53 Correctable Fault Location Register cache Correctable Fault Location Register52 Correctable Fault Location Register cache C15, Build Options 2 Register To access the Build Options 1 Register, write CP15 withBuild Options Registers C15, Build Options 1 RegisterAtcmes 55 Build Options 2 RegisterNoicache NodcacheNompu BtcmesNoie NofpuAxibusparity To access the Build Options 2 Register, write CP15 withNoharderrorcach DcacheesPrefetch Unit About the prefetch unit Disabling program flow prediction Branch predictionConfiguring the branch predictor Branch predictorIncorrect predictions and correction Return stack Events and Performance Monitor Event Bit position Update ValueAbout the events Event bus interface bit functionsETMEXTOUT1 ETMEXTOUT0Dual issue case B1, B2, F2 load/store, F2D Non-cacheable access on AXI master busInstruction cache access But with different attributes Dual issue case a branchTCM correctable ECC error reported by prefetch unit Yes TCM correctable ECC error reported by load/store unit YesAbout the PMU 2shows how the bit values correspond with the Pmnc Register Performance monitoring registersPerformance monitoring registers are described 1 c9, Performance Monitor Control RegisterPmnc Register bit functions 2 c9, Count Enable Set RegisterTo access the Cntens Register, read or write CP15 with 3 c9, Count Enable Clear RegisterCntens Register bit functions Bits Field Function Cntenc Register bit functions Bits Field Function To access the Cntenc Register, read or write CP15 withCycle counter enable clear 4 c9, Overflow Flag Status RegisterTo access the Flag Register, read or write CP15 with 5shows how the bit values correspond with the Flag Register5 c9, Software Increment Register 313 Reserved RAZ on reads, Sbzp on writes Increment Counter To access the Swincr Register, read or write CP15 with6 c9, Performance Counter Selection Register Swincr Register bit functions Bits Field Function7 c9, Cycle Count Register 8 c9, Event Selection RegisterSEL EVTSELx Register bit functions To access the EVTSELx Register, read or write CP15 with10 c9, User Enable Register 9 c9, Performance Monitor Count RegistersUseren Register bit functions 11 c9, Interrupt Enable Set Register Ccnt overflow interrupt enable10 Intens Register bit functions Bits Field Function 12 c9, Interrupt Enable Clear Register Ccnt overflow interrupt enable bit11 Intenc Register bit functions Bits Field Function To access the Intenc Register, read or write CP15 with Use of the event bus and counters Event bus interfaceMPU faults on MPU software-accessible registers onMemory Protection Unit Default memory map About the MPUTrue Subregions Memory regionsRegion base address Region sizeRegion Region access permissionsRegion attributes Overlapping regionsExample of using subregions Example of using regions that overlapTCM regions Background regionsMemory types Using memory typesARM DDI 0363E TEX20, C, and B encodings Description Memory Type Shareable? Region attributes1BB Cacheable memory policiesOn page 7-2shows the default memory map MPU interaction with memory systemFollowing code is an example of disabling the MPU Permission fault MPU faultsBackground fault Permission fault Alignment fault Background faultOn page 4-5shows the CP15 registers that control the MPU MPU software-accessible registersLevel One Memory System About the L1 memory system L1 memory system block diagram About the error detection and correction schemes Parity Bit ECC onParity Read-Modify-Write Error checking and correctionHard errors Bit ECCError correction Correct inlineCorrect-and-retry MPU faults Fault handlingFaults Classes of fault that can occur areExternal faults Cache and TCM parity and ECC errorsTCM external faults Abort exceptions Fault status informationDebug events Precise and imprecise abortsPrecise abort exceptions Imprecise abort exceptionsUsage models Correctable errors Types of aborts Conditions Source Precise FatalAXI ARM DDI 0363E TCM attributes and permissions About the TCMsAtcm and Btcm configuration TCM internal error detection and correctionHandling TCM parity errors on Handling TCM ECC errors on Handling TCM parity errors Handling TCM ECC errorsTCM arbitration External TCM errors TCM initializationTCM port protocol AXI slave interfaces for TCMs Store buffer About the cachesStore buffer draining Cache maintenance operationsStore buffer merging Store buffer behaviorError build options Cache error detection and correctionAddress decoder faults Handling cache parity errorsCache parity error behavior Value Behavior Cache ECC error behavior Value Behavior Handling cache ECC errorsErrors on evictions Errors on instruction cache readErrors on data cache read Errors on data cache writeInvalidate all instruction cache Clean data cache by set/way Tag RAM Cache RAM organizationTag RAM Dirty RAM on Data RAM onOrganization of a dirty RAM line Dirty RAMData RAM Cache sizes and tag RAM organization Tag RAM organizationNonsequential read operation performed with one RAM access Data RAM sizes without parity or ECC implemented 13 Data cache RAM bits, with parity Description 15 Data cache data RAM sizes with ECC Cache size Data RAMs Cache interaction with memory systemDisabling or enabling all of the caches Following code is an example of enabling cachesDisabling or enabling error checking Disabling or enabling instruction cacheDisabling or enabling data cache MCR p15 R0, c1 Write System Control Register Internal exclusive monitor Memory types and L1 memory system behavior Data-cache error events Error detection eventsTCM error events Instruction-cache error eventsARM DDI 0363E Level Two Interface About the L2 interface AXI master interface 1shows the AXI master interface attributesAttribute Value Comments Write response Identifiers for AXI bus accessesOutstanding write/read access on different IDs Outstanding write accesses with the same IDAruserm and Awuserm encodings Eviction bufferMemory attributes Arcachem and Awcachem encodings Encoding a MeaningMemory system implications for AXI accesses AXI master interface transfers Strongly Ordered and Device transactions onLinefills on Address20 Restrictions on AXI transfersStrongly Ordered and Device transactions Non-cacheable LdrbLdrh from Strongly Ordered or Device memory Address30 LDR or LDM that transfers one registerLDM5, Strongly Ordered or Device memory Address40 LDM that transfers five registersStrh to Strongly Ordered or Device memory Address20 Strb to Strongly Ordered or Device memory Address40STR or STM of one register STM of seven registersFirst Wstrbm Linefills Cache line write-back evictionNon-cacheable reads 15 LDR or LDM1 from Non-cacheable Normal memory Address20 14 Ldrh from Non-cacheable Normal memory Address20Non-cacheable or write-through writes AXI transaction splitting 20 AXI transaction splitting, data in two cache lines Normal write mergingExample 9-1 Write merging ARM DDI 0363E AXI slave interface for cache RAMs AXI slave interfaceTCM parity and ECC support Cache parity and ECC supportAXI slave control 25 AXI slave interface attributes AXI slave characteristicsEnabling or disabling AXI slave accesses Accessing RAMs using the AXI slave interface TCM RAM access on Cache RAM access on26 RAM region decode AxUSERS bit One-hot RAM select RAM selected TCM RAM accessARADDRSMSB, see Table 27 TCM chip-select decode Btcm portsCache RAM access Memory map when accessing the cache RAMsThis section contains the following 0001 Bank 0010 0100 1000 Data RAM access0010 Bank 0100 1000 31 Cache data RAM bank/address decode Inputs ARADDRS181535 Data format, data cache, with ECC Data bit Description 34 Data format, instruction cache, with ECCTag RAM access ARM DDI 0363E 43 Dirty register format, with ECC Data bit Description Dirty RAM accessARADDRS1815 = 4b1111 Other examples of accessing cache RAMsAbout power control on Power management on Power ControlAbout power control Shutdown mode Run modeStandby mode Dormant modeCommunication to the Power Management Controller Debug state on Cache debug on DebugProtocol converter Debug systemsDebug host Protocol converter Debug target Debug hostProgramming the debug unit About the debug unitHalting debug-mode debugging Monitor debug-mode debuggingAll other state information associated with the debug unit Coprocessor registers summary 11.3.2 CP14 access permissionsDebug register interface Coprocessor registersDebug memory-mapped registers Offset Register Access Mnemonic Description Hex NumberMemory-mapped registers Instruction Mnemonic DescriptionMemory addresses for breakpoints and watchpoints Privilege of memory access permission Power domainsEffects of resets on debug registers APB port access permissionsOther registers External debug interface access permissions RegistersLock Other Debug registers11.4.2 CP14 c0, Debug ID Register Accessing debug registersDebug register descriptions 6shows the CP14 debug register mapDebug ID Register functions WRPBRP 11.4.4 CP14 c0, Debug Self Address Offset Register To use the Debug ID Register, read CP14 c0 with11.4.3 CP14 c0, Debug ROM Address Register To use the Debug ROM Address Register, read CP14 c0 withDebug Self Address Offset Register functions Debug Self Address Offset Register format10 Debug Status and Control Register functions 11.4.5 CP14 c1, Debug Status and Control RegisterFlag is set to 1 on entry to debug state Execute ARM instruction enable bit = disabled, this is the reset valueARM MOE DTR access modeData Transfer Register Reserved RAZ Watchpoint Fault Address Register12 Watchpoint Fault Address Register functions Vector Catch RegisterSVC 14 Debug State Cache Control Register functions Bits Field Reset Description ValueDebug State Cache Control Register Instruction Transfer RegisterDebug Run Control Register 15 Debug Run Control Register functions315 Reserved Breakpoint Control Registers Breakpoint Value Registers17 Breakpoint Control Registers functions BVR2220 Meaning +0 is accessedCorresponding instruction address breakpoint 18 Meaning of BVR bitsWatchpoint Value Registers Watchpoint Control Registers19 Watchpoint Value Registers functions Bits Description 20 Watchpoint Control Registers functions 11 Watchpoint Control Registers formatOperating System Lock Status Register Accessed21 OS Lock Status Register functions Authentication Status Register23 Prcr functions Device Power-down and Reset Control RegisterDevice Power-down and Reset Status Register = Dbgnopwrdwn is LOW. This is the reset value24 Prsr functions 15 Prsr formatProcessor ID Registers Management registersClaim Registers Claim Tag Set Register27 Claim Tag Set Register functions Bits Field Function Lock Status Register Lock Access Register318 Reserved RAZ or Sbzp Claim tag clear Reset value is Claim Tag Clear RegisterDevice Type Register Debug Identification Registers30 Device Type Register functions Bits Value Description 32 Fields in the Peripheral Identification RegistersField Size Description 33 Peripheral ID Register 0 functions37 Peripheral ID Register 4 functions 34 Peripheral ID Register 1 functions35 Peripheral ID Register 2 functions 36 Peripheral ID Register 3 functions1022 1020Component Identification Register 1021Software debug event Debug eventsWatchpoint debug events Halting debug eventBehavior of the processor on debug events Debug event priorityDebug exception Four CP15 registers that record abort information are 40shows the values in the link register after exceptionsFollowing sections describe Effect of debug exceptions on CP15 registers and WfarAvoiding unrecoverable states 41 Read PC value after debug state entry Debug statePrivilege on Entering debug state41 Read PC value after debug state entry Debug event Behavior of the PC and Cpsr in debug statePrivilege Accessing registers and memoryExecuting instructions in debug state Writing to the Cpsr in debug stateExceptions in debug state Coprocessor instructionsEffect of debug state on non-invasive debug Effects of debug events on processor registersLeaving debug state Precise Data abortImprecise Data Abort Imprecise Data Aborts on entry and exit from debug stateSets the DSCR1 core restarted flag to Cache coherency in debug state Cache debugThis section describes cache debug. It consists Cache pollution in debug stateExternal debug interface APB signalsMiscellaneous debug signals This section describes the miscellaneous debug signalsNon-invasive debug permitted Authentication signalsChanging the authentication signals 42 Authentication signal restrictions Dbgen aIssue an Instruction Synchronization Barrier ISB instruction Example 11-1 Executing an ARM instruction through the ITR Using the debug functionalityDebug communications channel Rules for accessing the DCCExample 11-4 Target to host data transfer host end Software access to the DCCDebugger access to the DCC Example 11-5shows the code for host-to-target data transferExample 11-6 Polling the DCC host end Programming breakpoints and watchpointsThis section describes the following operations Programming simple breakpoints and the byte address selectExample 11-7 Setting a simple breakpoint Setting a simple aligned watchpointExample 11-8 Setting a simple aligned watchpoint Setting a simple unaligned watchpointNot required Example 11-9 Setting a simple unaligned watchpoint45shows some examples Single-steppingDebug state entry Example 11-10 Single-stepping off an instructionExample 11-11 Entering debug state Example 11-12 Leaving debug state Debug state exitExample 11-13 Reading an ARM register Accessing registers and memory in debug stateThis section describes the following Reading and writing registers through the DCCExample 11-16shows the code for reading the Cpsr Reading the PC in debug stateExample 11-15shows the code to read the PC Reading the Cpsr in debug stateExample 11-17 Writing the Cpsr Example 11-19 Checking for an abort after memory accessReading memory Example 11-18shows the code for reading a byte of memoryExample 11-21 Reading a word of memory Example 11-20 Reading a block of bytes of memoryFast register read/write Example 11-22 Changing the DTR access modeExample 11-23 Reading registers in stall mode Example 11-24 Writing registers in stall modeExample 11-25 Reading a block of words of memory Fast memory read/writeExample 11-27 Reading a coprocessor register Accessing coprocessor registers11-70 Debugging systems with energy management capabilities Emulating power down11-72 FPU Programmer’s Model About the FPU programmer’s model FPU functionalityAbout the VFPv3-D16 architecture FPU views of the register bank General-purpose registersSystem registers VFPv3 architecture describes the following system registers1shows the VFP system registers in the Cortex-R4F FPU This is a change in VFPv3 compared to VFPv2 All hardware ID information is privileged access onlyFpsid is privileged access only Mvfr registers are privileged access onlyRmode Floating-Point Status and Control Register, FpscrFpscr Register bit functions DNMDNM IXE RAZ UFE OFE DZE IOE IDC Floating-Point Exception Register, FpexcLEN IDE RAZMVFR0 Register bit functions Media and VFP Feature Registers, MVFR0 and MVFR1Floating-Point Exception Register bit functions DEXFull denormal arithmetic supported for VFP MVFR1 Register bit functionsDefault NaN mode Full-compliance mode Flush-to-zero mode Default NaN modeFull-compliance mode Flush-to-zero modeNaN handling Compliance with the Ieee 754 standardComplete implementation of the Ieee 754 standard Ieee 754 standard implementation choicesCDP ComparisonsUnderflow QNaN and SNaN handlingExceptions Integration Test Registers About Integration Test Registers Programming and reading Integration Test Registers Software access using APBItmiscin Register ItctrlItetmif ItmiscoutProcessor integration testing 13121110 Performing integration testing Using the Integration Test RegistersItetmif Register bit assignments Bits Name Function Itetmif Register ETM interfaceItmiscout Register Miscellaneous Outputs Itmiscin Register Miscellaneous InputsItmiscout Register bit assignments Bits Name Function Etmextout Integration Mode Control Register ItctrlBits Name Function DbgrestartIntmode Bits Access Reset value Name Function7shows the fields of the Itctrl Register RAZ/SBZPMultiplies on Divide on Branches on Cycle Timings and Interlock BehaviorDual issue on Instruction execution overview About cycle timings and interlock behaviorDefinition of terms Following sequence where R1 is a Late Reg takes two cyclesFlag-setting instructions Conditional instructionsAssembler language syntax Takes three cycles because of the result latency of R1 Register interlock examplesInstruction Behavior Sequence Takes two cycles because there are no register dependenciesData processing instructions Cycle counts if destination is not PCCycle counts if destination is the PC Example interlocks ShifterRegister controlled shifts QADD, QDADD, QSUB, and Qdsub instructions SEL Media data-processingUSAD8 instruction Sum of Absolute Differences SADInstruction sequence Behavior Result of the USAD8 instructionUmlals Multiplies14-13 Divide Branches 10 Branch instruction cycle timing behaviorExample instruction Cycles Memory Comments All MSR instructions to the Spsr Mode changingProcessor state updating instructions All MRS instructions13shows the cycle timing behavior for loads to the PC Single load and store instructionsBase register update 13 Cycle timing behavior for loads to the PCExample instruction Cycles Memory Result Comments Latency 14-19 Load and Store Double instructions Register offset, then 3-issue cyclesWrite-back Load and Store Multiple instructionsCorrect condition prediction and incorrect Load Multiples, where the PC is in the register listCorrect condition prediction and correct Return stack prediction14-23 RFE and SRS instructions Clrex Synchronization instructionsSome instructions such as cache operations take more cycles Coprocessor instructionsPrefetch Abort Undefined Instruction SVC formerly SWIMiscellaneous instructions Floating-point register transfer instructions Blocking and serializingSerializing 2,2 Floating-point load/store instructionsBit aligned address Not aligned4,5 2,3Floating-point single-precision data processing instructions Floating-point double-precision data processing instructions Dual issue Dual issue rules Permitted combinations onDual issue rules Dual issue First instruction Second instruction Case Permitted combinations28 Permitted instruction combinations Case F2Db Case F2stbAny single-precision CDPi, excluding Multiply-accumulate instructionsoProcessor timing on Processor timing parameters on AC CharacteristicsProcessor timing Clock uncertainty 50% Processor timing parametersInput port timing parameters Clock uncertainty 10%3shows the timing parameters for the interrupt input ports 4shows the input timing parameters for the AXI master portClock uncertainty 60% Rreadys 5shows the input timing parameters for the AXI slave port7shows the input timing parameters for the ETM input ports 6shows the input timing parameters for the debug input ports8shows the timing parameters for the test input ports Clock uncertainty 65%Clock uncertainty 40% 11shows the timing parameters for the interrupt output ports Output ports timing parametersWrite response channel Clock uncertainty 60% 13shows the timing parameters for the AXI slave output portsBRESPS10 Clock uncertainty 45% 16shows the timing parameters for the test output portsFpidc 18shows the timing parameters for the FPU output signals15-13 FPU signals on page A-23 Processor Signal DescriptionsAbout the processor signal descriptions AnyFrom any clock Global signals Table A-1 Global signalsSignal Direction Clocking Description Information Configuration signalsTable A-2shows the processor configuration signals Table A-2 Configuration signalsTie High for odd parity Tie LOW for even parityRMWENRAM10b Interrupt signals, including VIC interface signals L2 interface signals Table A-4 AXI master port signals for the L2 interfaceAXI master port Protection signals provide addition information about a bus Identification tag for the write data group of signalsIdentification tag for the write response signal Identification tag for the read address group of signalsAXI slave port AXI master port error detection signalsTable A-5 AXI master port error detection signals Table A-6 AXI slave port signals for the L2 interfaceOne to 16. a four bit binary value minus one determines Protection information, privileged/normal access. AWPROT0AXI specification Protection information, privileged/normal access. ARPROT0Table A-7 AXI slave port error detection signals AXI slave port error detection signalsATCM, one hot. AWUSERS30 signal is not part Standard AXI specificationTCM interface signals Table A-8shows the Atcm port signalsTable A-9shows the B0TCM port signals Table A-10shows the B1TCM port signals Table A-10 B1TCM port signals= DMA Write parity or ECC code for B1TCM B1TCM RAM access is sequentialAddress for B1TCM data RAM Write data for B1TCM data RAMDual core interface signals Table A-11shows the dual redundant core interface signalsTable A-11 Dual core interface signals Debug interface signals Table A-13shows the debug miscellaneous signalsTable A-12 Debug interface signals Input Tie-off Debug self-address offset valid Table A-13 Debug miscellaneous signalsInput Tie-off Debug ROM physical address valid Input Tie-off Debug self-address offsetETM interface signals Table A-14shows the ETM interface signalsTable A-14 ETM interface signals Test signals Table A-15shows the test signalsTable A-15 Test signals Table A-16shows the Mbist signals Mbist signalsTable A-17shows the validation signals Validation signalsTable A-18 FPU signals FPU signalsECC scheme selection guidelines on page B-2 ECC SchemesECC scheme selection guidelines Clarified little-endian format NCPUHALT removed from timing diagram Added sectionsRevisions Clarified byte-invariant big-endian formatChange Location Table C-1 Differences between issue B and issue CNo technical changes Table C-2 Differences between issue C and issue DBase register write-back GlossaryAbort, and an internal or External Abort See also Data Abort, External Abort and Prefetch AbortSee Advanced Microcontroller Bus Architecture See also Advanced High-performance BusSee Advanced High-performance Bus That are divisible by four and two respectivelyCompleted transfer Active read transactionActive transfer Active write transactionWrite ID width Read ID widthRead issuing capability Write ID capabilitySee also Beat See also BurstBus Accesses are expected to be word-alignedAccessed in parallel during a cache look-up See also Word-invariantSee also Dirty See also Clean See Embedded Trace Macrocell Precision and the fraction is all zeros An instruction that is architecturally UndefinedBy individual implementations Option chosen does not affect software compatibilityResult of attempting to access invalid instruction memory Serviced while normal program execution is suspendedSee also Halt mode See Cold resetSee Boundary scan chain Or equal to 1 and is not restricted to being a power of twoSee Should Be One See Should Be ZeroUser trap handler is executed See Debug test access portIncrement of +2 Destination precisionA processor Expected behavior for an unaligned accessBit for the exception is set Processor-specific. a victim is also known as a cast outCache terminology diagram

Cortex-R4 and Cortex-R4F Technical Reference Manual

Chapter 1

Introduction

Chapter 2

Programmer’s Model

ARM DDI 0363E