Level Two Interface

LDM that transfers five registers

Table 9-7shows the values of ARADDRM, ARBURSTM, ARSIZEM, and ARLENM for a Non-cacheable LDM that transfers five registers (an LDM5) in Strongly Ordered or Device memory.

Table 9-7 LDM5, Strongly Ordered or Device memory

Address[4:0]

ARADDRM

ARBURSTM

ARSIZEM

ARLENM

 

 

 

 

 

0x00 (word 0)

0x00

Incr

32-bit

5 data transfers

 

 

 

 

 

0x04 (word 1)

0x04

Incr

32-bit

5 data transfers

 

 

 

 

 

0x08 (word 2)

0x08

Incr

32-bit

5 data transfers

 

 

 

 

 

0x0C (word 3)

0x0C

Incr

32-bit

5 data transfers

 

 

 

 

 

Note

A load-multiple from address 0x1, 0x2, 0x3, 0x5, 0x6, 0x7, 0x9, 0xA, 0xB, 0xD, 0xE, or 0xF generates an alignment fault.

ARM DDI 0363E

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9-10

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ARM R4F, r1p3 manual LDM that transfers five registers, LDM5, Strongly Ordered or Device memory Address40