ARM r1p3, R4F manual TCM parity and ECC support, Cache parity and ECC support, AXI slave control

Level Two Interface

9.4.2TCM parity and ECC support

The TCMs can support parity or ECC, as described in TCM internal error detection and correction on page 8-14.If a write transaction is issued to the AXI slave, the slave interface calculates the required parity or ECC bits to store to the TCM. ECC schemes require the AXI slave to perform a read-modify-write sequence if the write data width is smaller than the ECC chunk size.

If a read transaction is issued to the AXI slave, the slave interface reads the parity or ECC bits and, if error checking is enabled for the appropriate TCM, checks the data for errors. If the interface detects a correctable error, it corrects it inline and returns the correct data on the AXI bus. It does not update the data in the TCM to correct it. If the interface detects an uncorrectable error, it generates a SLVERR error response to the AXI transaction.

9.4.3External TCM errors

If an error response is given to a TCM access from the AXI slave interface, and external errors are enabled for the appropriate TCM port, the AXI slave returns a SLVERR response to the AXI transaction.

The AXI slave ignores late-error and retry responses from the TCM.

9.4.4Cache parity and ECC support

When the caches support parity or ECC, the AXI slave interface can read and write the parity or ECC code bits directly. No errors are detected automatically, and on writes the AXI slave does not automatically generate the correct parity or ECC code values.

Note

The AXI slave interface provides read/write access to the cache RAMs for functional test. It is not suitable for preloading the caches.

9.4.5AXI slave control

By default, both privileged and non-privileged accesses can be made to the Cortex-R4 TCM RAMs through the AXI slave port. To disable non-privileged accesses, you can set bit [1] in the Slave Port Control Register. You can disable all slave accesses by setting bit [0] of the register. See c11, Slave Port Control Register on page 4-59.

Access to the cache RAMs can only be made when bit [24] of the Auxiliary Control Register is set. By default, only privileged accesses can be made to the cache RAMs, but you can enable non-privileged accesses by setting bit [23] of the Auxiliary Control Register. When cache RAM access is enabled, both caches are treated as if they were not enabled. See Auxiliary Control Registers on page 4-38.

The AXI access is given a SLVERR error response when access is not permitted.

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