ARM R4F Cache debug, This section describes cache debug. It consists, Cache usage profiling

Debug

11.9Cache debug

This section describes cache debug. It consists of:

•Cache pollution in debug state

•Cache coherency in debug state

•Cache usage profiling.

11.9.1Cache pollution in debug state

If bit [0] of the Debug State Cache Control Register (DSCCR) is set to 0 while the processor is in debug state, then the L1 data cache does not perform any line fill.

Note

No special feature is required to prevent L1 instruction cache pollution because instruction side fetches cannot occur while in debug state.

11.9.2Cache coherency in debug state

The debugger can update memory while in debug state:

•to replace an instruction with a BKPT, or to restore the original instruction

•to download code for the processor to execute on leaving debug state.

The debugger can maintain cache coherency in both these situations with the following features:

•If bit [2] of the DSCCR is set to 0 while the processor is in debug state, then the processor treats any memory access that hits in L1 data cache as write-through, regardless of the memory region attributes. This guarantees that the L1 instruction cache can see the changes to the code region without the debugger executing a time-consuming and device-specific sequence of cache clean operations.

•After the code is written to memory, the debugger can execute either a CP15 instruction cache invalidate all operation, or a CP15 instruction cache invalidate line operation.

Note

The processor can normally execute CP15 instruction cache invalidate all operation or CP15 instruction cache invalidate line operation only in Privileged mode. However, in debug state the processor can execute these instructions even when invasive debug is not permitted in Privileged mode. This exception to the rule enables the debugger to maintain coherency.

11.9.3Cache usage profiling

You can obtain cache usage profiling information using the Performance Monitoring Unit (PMU). The processor can count cache accesses and misses over a period of time. See Chapter 6 Events and Performance Monitor.

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