System Control Coprocessor

CRn Opcode_1 CRm Opcode_2

c0

c7

c15

0c0

1c0

2c0

0

0c5

1

0

1

0

0

Cache Type Register

Current Cache Size Identification Register Current Cache Level Identification Register Cache Size Selection Register

Cache Operations Registers Invalidate all Data Cache Register

Read-only

 

Read/write

 

Write-only

See description of cache operations for implemented CRm and Opcode_2 values

Accessible in User mode

See description of cache operations for operations with User mode access

Figure 4-3 Cache control and configuration registers

Cache control and configuration registers behave as:

a set of numbers, with values that describe aspects of the caches

a set of bits that enable specific cache functionality

a set of operations that act on the caches.

4.1.5TCM control and configuration

The TCM control and configuration registers:

inform the processor about the status of the TCM regions

define TCM regions.

The TCM control and configuration registers consist of two read-only registers and two read/write registers. Figure 4-4shows the arrangement of registers.

CRn

Opcode_1

c0

 

 

 

 

0

 

c9

 

 

 

 

0

 

 

CRm

Opcode_2

 

 

 

 

 

 

 

 

 

 

 

 

 

TCM Type Register

 

 

c0

 

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BTCM Region Register

 

 

c1

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ATCM Region Register

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCM Selection Register

 

 

c2

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read-only

 

Read/write

 

Write-only

Accessible in User mode

Figure 4-4 TCM control and configuration registers

TCM control and configuration behaves in three ways:

as a set of numbers, with values that describe aspects of the TCMs

as a set of bits that enable specific TCM functionality

as a set of addresses that define the memory locations of data stored in the TCMs.

4.1.6System performance monitor

The performance monitor registers:

control the monitoring operation

count events.

The system performance monitor consists of 12 read/write registers. Figure 4-5 on page 4-7shows the arrangement of registers in this functional group.

ARM DDI 0363E

Copyright © 2009 ARM Limited. All rights reserved.

4-6

ID013010

Non-Confidential, Unrestricted Access

 

Page 90
Image 90
ARM R4F, r1p3 manual TCM control and configuration, System performance monitor