ARM r1p3, R4, R4F

List of Tables

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Table 8-6 Tag RAM bit descriptions, no parity or ECC ............................................................................. 8-26

Table8 -7 Cache sizes and tag RAM organization .................................................................................... 8-27

Table8 -8 Organization of a dirty RAM line ............................................................................................... 8-27

Table 8-9 Instruction cache data RAM sizes, no parity or ECC ................................................................ 8-29

Table 8-10 Data cache data RAM sizes, no parity or ECC ......................................................................... 8-29

Table 8-11 Instruction cache data RAM sizes, with parity .......................................................................... 8-29

Table 8-13 Data cache RAM bits, with parity .............................................................................................. 8-30

Table 8-14 Instruction cache data RAM sizes with ECC ............................................................................. 8-30

Table8 -12 Data cache data RAM sizes, with parity ................................................................................... 8-30

Table 8-15 Data cache data RAM sizes with ECC ...................................................................................... 8-31

Table8 -16 Data cache RAM bits, with ECC ............................................................................................... 8-31

Table 8-17 Memory types and associated behavior ................................................................................... 8-35

Table9 -1 AXI master interface attributes .................................................................................................... 9-3

Table9 -2 ARCACHEM and AWCACHEM encodings ................................................................................. 9-5

Table 9-3 ARUSERM and AWUSERM encodings ...................................................................................... 9-5

Table 9-4 Non-cacheable LDRB ................................................................................................................. 9-8

Table 9-5 LDRH from Strongly Ordered or Device memory ....................................................................... 9-9

Table 9-6 LDR or LDM1 from Strongly Ordered or Device memory ........................................................... 9-9

Table 9-7 LDM5, Strongly Ordered or Device memory ............................................................................. 9-10

Table 9-8 STRB to Strongly Ordered or Device memory .......................................................................... 9-11

Table 9-9 STRH to Strongly Ordered or Device memory .......................................................................... 9-11

Table 9-10 STR or STM1 to Strongly Ordered or Device memory ............................................................. 9-12

Table 9-11 STM7 to Strongly Ordered or Device memory to word 0 or 1 ................................................... 9-12

Table 9-12 Linefill behavior on the AXI interface ........................................................................................ 9-13

Table 9-13 Cache line write-back ................................................................................................................ 9-13

Table 9-14 LDRH from Non-cacheable Normal memory ............................................................................ 9-13

Table 9-15 LDR or LDM1 from Non-cacheable Normal memory ................................................................ 9-14

Table 9-16 LDM5, Non-cacheable Normal memory or cache disabled ...................................................... 9-14

Table 9-17 STRH to Cacheable write-through or Non-cacheable Normal memory .................................... 9-15

Table 9-18 STR or STM1 to Cacheable write-through or Non-cacheable Normal memory ........................ 9-16

Table 9-19 AXI transaction splitting, all six words in same cache line ........................................................ 9-16

Table 9-20 AXI transaction splitting, data in two cache lines ...................................................................... 9-17

Table 9-21 Non-cacheable LDR or LDM1 crossing a cache line boundary ................................................ 9-17

Table 9-22 Cacheable write-through or Non-cacheable STRH crossing a cache line boundary ................ 9-17

Table 9-23 AXI transactions for Strongly Ordered or Device type memory ................................................ 9-18

Table 9-24 AXI transactions for Non-cacheable Normal or Cacheable write-through memory .................. 9-18

Table9-25 AXI slave interface attributes .................................................................................................... 9-22

Table9 -26 RAM region decode .................................................................................................................. 9-24

Table9 -27 TCM chip-select decode ........................................................................................................... 9-25

Table 9-28 MSB bit for the different TCM RAM sizes ................................................................................. 9-25

Table 9-29 Cache RAM chip-select decode ................................................................................................ 9-26

Table 9-30 Cache tag/valid RAM bank/address decode ............................................................................. 9-26

Table 9-32 Data format, instruction cache and data cache, no parity and no ECC .................................... 9-27

Table 9-31 Cache data RAM bank/address decode ................................................................................... 9-27

Table 9-33 Data format, instruction cache and data cache, with parity ...................................................... 9-28

Table 9-34 Data format, instruction cache, with ECC ................................................................................. 9-28

Table 9-35 Data format, data cache, with ECC ........................................................................................... 9-28

Table9-36 Tag register format for reads, no parity or ECC ........................................................................ 9-29

Table9 -37 Tag register format for reads, with parity .................................................................................. 9-29

Table9 -38 Tag register format for reads, with ECC ................................................................................... 9-29

Table 9-39 Tag register format for writes, no parity or ECC ....................................................................... 9-30

Table 9-40 Tag register format for writes, with parity .................................................................................. 9-30

Table 9-41 Tag register format for writes, with ECC ................................................................................... 9-30

Table 9-42 Dirty register format, with parity or with no error scheme ......................................................... 9-31

Table9 -43 Dirty register format, with ECC ................................................................................................. 9-31

Table1 1-1 Access to CP14 debug registers ............................................................................................... 11-5

Table 11-2 CP14 debug registers summary ............................................................................................... 11-6

Table1 1-3 Debug memory-mapped registers ............................................................................................ 11-6

Table 11-4 External debug interface access permissions ........................................................................... 11-9

Table 11-5 Terms used in register descriptions ........................................................................................ 11-10