ARM r1p3, R4F manual C15, nVAL Debug Request Enable Clear Register

System Control Coprocessor

Table 4-48 nVAL Reset Enable Clear Register bit functions (continued)

Bits	Field	Function
[2]	P2	PMC2 overflow reset request
[1]	P1	PMC1 overflow reset request
[0]	P0	PMC0 overflow reset request

To access the nVAL Reset Enable Clear Register, read or write CP15 with:

MRC p15, 0, <Rd>, c15, c1, 6 ; Read nVAL Reset Enable Clear Register MCR p15, 0, <Rd>, c15, c1, 6 ; Write nVAL Reset Enable Clear Register

On reads, this register returns the current setting. On writes, overflow reset requests that are currently enabled can be disabled.

For more information of how to enable reset requests on counter overflows, and how the requests are signaled, see c15, nVAL Reset Enable Set Register on page 4-64.

c15, nVAL Debug Request Enable Clear Register

The nVAL Debug Request Enable Clear Register disables overflow debug requests from any of the PMC Registers, PMC0-PMC2, and CCNT, that are enabled.

The nVAL Debug Request Enable Clear Register is:

•A read/write register.

•Always accessible in Privileged mode. The USEREN Register determines access, see c9, User Enable Register on page 6-15.

Figure 4-51shows the bit arrangement for the nVAL Debug Request Enable Clear Register.

31

C

3 2 1 0

Reserved

Cycle count overflow	Performance monitor counter overflow	P2
		P1
debug request disable	debug request disables
		P0

Figure 4-51 nVAL Debug Request Enable Clear Register format

Table 4-49shows how the bit values correspond with the nVAL Debug Request Enable Clear Register.

Table 4-49 nVAL Debug Request Enable Clear Register bit functions

Bits	Field	Function
[31]	C	CCNT overflow debug request
[30:3]	Reserved	UNP or SBZP
[2]	P2	PMC2 overflow debug request
[1]	P1	PMC1 overflow debug request
[0]	P0	PMC0 overflow debug request

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