Introduction

Iss

Register

read,

address

generation, and

instruction

issue

Ex1

DC1

EX1

F0

Ex2

DC2

EX1

F1

Wr

Wr

F2

Ret

Fwr

Load/store

pipeline

Data

processing

pipeline

Floating point

pipeline

Mispredicted direct branches

Exception flush and mispredicted

indirect branches

Figure 1-4 Cortex-R4F Issue and Execution pipeline stages

The names of the common pipeline stages and their functions are:

Iss

Register read and instruction issue to execute stages.

Ex

Execute stages.

Wr

Write-back of data from the execution pipelines.

Ret

Instruction retire.

The names of the load/store pipeline stages and their functions are:

DC1

First stage of data memory access.

DC2

Second stage of data memory access.

The names of the floating point pipeline stages and their functions are:

F0

Floating point register read.

F1

First stage of floating point execution.

F2

Second stage of floating point execution.

Fwr

Floating point writeback.

The pipeline structure provides a pipelined 2-cycle memory access and single-cycle load-use penalty. This enables integration with slow RAM blocks and maintains good CPI at reasonable frequencies.

ARM DDI 0363E

Copyright © 2009 ARM Limited. All rights reserved.

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ARM R4F, r1p3 manual Iss, Execute stages, Write-back of data from the execution pipelines, Ret Instruction retire