ARM r1p3, R4, R4F 12.4 Modes of operation

FPU Programmer’s Model

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12.4 Modes of operation

The FPU provides three modes of operation to accommodate a variety of applications:

•Full-compliance mode

•Flush-to-zero mode

•Default NaN mode

12.4.1 Full-compliance mode

In full-compliance mode, the FPU processes all operations according to the IEEE 754 standard

in hardware.

12.4.2 Flush-to-zero mode

Setting the FZ bit, FPSCR[24], enables flush-to-zero mode. In this mode, the FPU treats all

subnormal input operands of arithmetic

CDP

operations as zeros in the operation. Exceptions that

result from a zero operand are signaled appropriately.

VABS

VNEG

, and

VMOV

are not considered

arithmetic

CDP

operations and are not affected by flush-to-zero mode. A result that is tiny, as

described in the IEEE 754 standard, for the destination precision is smaller in magnitude than

the minimum normal value before rounding and is replaced with a zero. The IDC flag,

FPSCR[7], indicates when an input flush occurs. The UFC flag, FPSCR[3], indicates when a

result flush occurs.

12.4.3 Default NaN mode

Setting the DN bit, FPSCR[25], enables default NaN mode. In this mode, the result of any

operation that involves an input NaN, or that generated a NaN result, returns the default NaN.

Propagation of the fraction bits is maintained only by

VABS

VNEG

, and

VMOV

operations. All other

CDP

operations ignore any information in the fraction bits of an input NaN.