Cycle Timings and Interlock Behavior
ARM DDI 0363E Copyright ©2009 ARM Limited. All rights reserved. 14-34
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14.23 Dual issue
To increase instruction throughput, the processor can issue certain pairs of instructions
simultaneously. This is called dual issue. When this happens, the instruction with the smaller
cycle count is assumed to execute in zero cycles. If a pair of instructions can be dual-issued, they
are always dual-issued unless dual-issuing is disabled, see Auxiliary Control Registers on
page 4-38. If one instruction of the pair is interlocked, both are interlocked.
This section describes:
•Dual issue rules
•Permitted combinations on page 14-35
14.23.1 Dual issue rules
The following rules apply to dual-issue instructions:
• Both instructions must be available to the issue stage at the same time. This is unlikely if
there are many branches.
• The second instruction must not use the PC as a source register unless it is B #immed.
• The first instruction must not use the PC as a destination register.
• Both instructions must belong to the same instruction set, ARM or Thumb.
• There must be no data dependency between the two instructions. That is, the second
instruction must not have any source registers that are destination registers of the first
instruction.