System validation, System performance monitor registers

												System Control Coprocessor
CRn	Opcode_1			CRm				Opcode_2
c9											Performance Monitor Control Register †

										0
			0			c12
			0			c12
											Count Enable Set Register †

										1
										1
											Count Enable Clear Register †
										2
										2
											Overflow Flag Status Register †
										3
										3
											Software Increment Register †
										4
										4
											Performance Counter Selection Register †
										5
										5
											Cycle Count Register †
			0		c13				0
			0		c13				0
											Event Select Register †
										1
										1
											Performance Count Register †
										2
										2
											User Enable Register
			0		c14				0
			0		c14				0
											Interrupt Enable Set Register
										1
										1
											Interrupt Enable Clear Register
										2
										2
		Read-only					Read/write				Write-only	Accessible in User mode


												† If enabled in User
												Enable Register

Figure 4-5 System performance monitor registers

System performance monitoring counts system events, such as cache misses, pipeline stalls, and other related features to enable system developers to profile the performance of their systems. It can generate interrupts when the number of events reaches a given value.

For more information on the programmer’s model of the performance counters see the ARM

Architecture Reference Manual.

See Chapter 6 Events and Performance Monitor for more information on the registers.

4.1.7System validation

The system validation registers extend the use of the system performance monitor registers to provide some functions for validation. You must not use them for other purposes. The system validation registers schedule and clear:

•resets

•interrupts

•fast interrupts

•external debug requests.

The system validation registers consist of nine read/write registers and one write-only register. Figure 4-6shows the arrangement of registers.

CRn c15

Opcode_1		CRm			Opcode_2
	0			c1				0
	0			c1				0

							1
							1

							2
							2

							3
							3

							4
							4

							5
							5

							6
							6

							7
							7

	0		c14			0
	0		c14			0

nVAL IRQ Enable Set Register †

nVAL FIQ Enable Set Register †

nVAL Reset Enable Set Register †

nVAL Debug Request Enable Set Register † nVAL IRQ Enable Clear Register †

nVAL FIQ Enable Clear Register †

nVAL Reset Enable Clear Register †

nVAL Debug Request Enable Clear Register †

Cache size override register

Read-only

Read/write

Write-only

Accessible in User mode

† If enabled in User Enable Register

Figure 4-6 System validation registers

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ARM R4F, r1p3 manual System validation, System performance monitor registers

Models: R4F r1p3 R4

Performance Count Register †

Figure 4-5 System performance monitor registers

Architecture Reference Manual.

4.1.7System validation

Figure 4-6 System validation registers

ARM DDI 0363E