AXI transaction splitting | ARM R4F, r1p3 guide

Level Two Interface

Table 9-18shows possible values of AWADDRM, AWBURSTM, AWSIZEM, and AWLENM for an STR or an STM that transfers one register, an STM1, to Normal memory through the AXI master port.

Table 9-18 STR or STM1 to Cacheable write-through or Non-cacheable Normal memory

Address[2:0]		AWADDRM	AWBURSTM	AWSIZEM	AWLENM	WSTRBM

0x0	(byte 0) (word 0)	0x00	Incr	32-bit	1 data transfer	b00001111

0x1	(byte 1)	0x01	Incr	64-bit	1 data transfer	b00011110

0x2	(byte 2)	0x00	Incr	64-bit	1 data transfer	b00111100

0x3	(byte 3)	0x03	Incr	64-bit	2 data transfers	b01111000
						b00000000

0x4	(byte 4) (word 1)	0x04	Incr	32-bit	1 data transfer	b11110000

0x5	(byte 5)	0x05	Incr	32-bit	2 data transfers	b11100000
						b00000001

0x6	(byte 6)	0x06	Incr	16-bit	1 data transfer	b11000000
		0x08	Incr	16-bit	1 data transfer	b00000011

0x7	(byte 7)	0x04	Incr	32-bit	2 data transfers	b10000000
						b00000111

9.3.7AXI transaction splitting

The processor splits AXI bursts when it accesses addresses across a cache line boundary, that is, a 32-byte boundary. An instruction which accesses memory across one or two 32-byte boundaries generates two or three AXI bursts respectively. The following examples show this behavior. They are provided as examples only, and are not an exhaustive description of the AXI transactions. Depending on the state of the processor, and the timing of the accesses, the actual bursts generated might have a different size and length to the examples shown, even for the same instruction.

For example, LDMIA R10, {R0-R5}loads six words from memory. The number of AXI transactions generated by this instruction depends on the base address, R10:

•If all six words are in the same cache line, there is a single AXI transaction. For example, for LDMIA R10, {R0-R5}with R10 = 0x1008, the interface might generate a burst of three, 64-bit read transfers, as shown in Table 9-19.

Table 9-19 AXI transaction splitting, all six words in same cache line

ARADDRM ARBURSTM ARSIZEM ARLENM

0x1008	Incr	64-bit	3 data transfers

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ARM R4F, r1p3 manual AXI transaction splitting

Contents

Cortex-R4 and Cortex-R4F Cortex-R4 and Cortex-R4F Technical Reference ManualCopyright 2009 ARM Limited. All rights reserved Chapter Introduction Cortex-R4 and Cortex-R4F Technical Reference Manual Chapter Processor Initialization, Resets, and Clocking Chapter AC Characteristics Appendix B ECC Schemes List of Tables Adfsr and Aifsr bit functions Dirty register format, with ECC 11-12 Example interlocks 14-11 Table A-18 FPU signals Table C-1 List of Figures Cache operations C7 format for Set and Way Vector Catch Register format 11-20 Feedback on Preface About this book Using this bookProduct revision status Identifies the major revision of the product Typographical Conventions Signals Timing diagrams This section lists publications by ARM and by third parties Further readingARM publications Other publications ARM welcomes feedback on this product and its documentation FeedbackFeedback on this product Feedback on this book Introduction About the processor About the architecture This section describes the main components of the processor Components of the processorDebug on System control coprocessor on Interrupt handling on Floating Point Unit Data Processing UnitLoad/store unit Prefetch unit Instruction and data caches Memory Protection UnitTCM interfaces 5 L2 AXI interfaces Error correction and detectionAXI master interface AXI slave interface System performance monitoring DebugETM interface Real-time debug facilities Interrupt handling System control coprocessorVIC port Low interrupt latency Changes Return from exception using data from the stack External interfaces of the processor Processor has the following interfaces for external accessAPB Debug interface ETM interface Test interface APB Debug interface Run mode Power managementStandby mode Shutdown mode Configurable options Configurable optionsAtcm VFP BtcmFPU includeda MPU Atcmpcen Configurable options at reset Feature Options RegisterB0TCMPCEN B1TCMPCEN B0TCMECEN AtcmecenB1TCMECEN Atcmrmw Execution pipeline stages Names of the pipeline stages and their functions areInstruction decode Iss First stage of data memory accessExecute stages Write-back of data from the execution pipelines Redundant core comparison Test features Product documentation, design flow, and architecture DocumentationDesign flow Configuration inputs Build configurationSoftware configuration Architectural information Advanced Microcontroller Bus Architecture protocol Processor identification Product revision information Revision field, Main ID Register Variant field, Main ID RegisterVariant field, Debug ID Register Revision field, Debug ID Register Registers on Programmer’s ModelProgram status registers on Exceptions on About the programmer’s model Instruction set states Switching stateARM state Thumb state Operating modes Data types Byte-invariantbig-endian format Little-endian format Memory formatsByte-invariant big-endian format Little-endian format Register set Registers Register mode identifiers Mode Mode identifier General registers and program counter N, Z, C, and V bits Program status registers IT bits Q bit J bit DNM bitsGE bits A bit E bitI and F bits Non-maskable fast interrupts on M40 Mode Visible state registers Thumb PSR mode bit valuesM bits Modification of PSR bits by MSR instructions ARM DDI 0363E Exceptions Reset on Interrupts on Aborts onException entry and exit summary Exception entry and exit summary Leaving an exception Taking an exception Reset InterruptsInterrupt request Fast interrupt request Program status registers on Non-maskable fast interruptsNon-maskable fast interrupts Interrupt controller Interrupt entry flowchart Interrupt entry sequence Prefetch aborts AbortsData aborts Precise aborts Aborts in Strongly Ordered and Device memory Imprecise aborts Supervisor call instruction Abort handler Breakpoint instruction Undefined instruction Exception vectors Acceleration of execution environments Architecture Reference Manual Unaligned and mixed-endian data access support Big-endian instruction support Resets on Processor Initialization, Resets, and ClockingReset modes on Initialization on Caches on TCM on Initialization1 MPU 2 CRS Caches 5 TCMPreloading TCMs DMA into TCM Write to TCM directly from debuggerPreloading TCMs with parity or ECC Using TCMs from reset NRESET ResetsPRESETDBGn NSYSPORESET Power-on reset Reset modes Processor reset Normal operationHalt operation AXI interface clocking Clock gating ClockingAXI interface clocking Clock gating System Control Coprocessor System control coprocessor functional groups About the system control coprocessor System control coprocessor register functions Function Register/operation Reference to descriptionFcse PID Configuration Region System control and configurationTCM control TCM Status System performance Performance monitoring Cache control and configuration MPU control and configuration System performance monitor TCM control and configuration System performance monitor registers System validation ARM DDI 0363E System control coprocessor registers Register allocationRAZ Undefined MPU Region Size Read/write Enable Undefined MPU Region Access Read/writeControl Undefined MPU Memory Region Read/write Number ARM DDI 0363E Undefined C3-c11 C12 Performance Monitor Read/write Event Select Read/write Unpredictable Performance MonitorCount Undefined Undefined C1-c15 C12 C0-c15 C13 C14 User Enable Read/writeRAZ,ignore Writes Context ID Read/write 7shows the arrangement of bits in the register 2 c0, Main ID Register 3 c0, Cache Type Register Main ID Register bit functionsBits Field Function 4 c0, TCM Type Register To access the Cache Type Register, read CP15 withCache Type Register bit functions Bits Field Function TCM Type Register bit functions Bits Field Function To access the MPU Type Register, read CP15 with To access the TCM Type Register, read CP15 with5 c0, MPU Type Register TCM Type Register bit functions Processor Feature Registers C0, Processor Feature Register 0, PFR06 c0, Multiprocessor ID Register C0, Processor Feature Register 1, PFR1 To access the Processor Feature Register 0 read CP15 withProcessor Feature Register 0 bit functions Processor Feature Register 1 bit functions 8 c0, Debug Feature Register To access the Processor Feature Register 1 read CP15 withDebug Feature Register 0 bit functions 3124 Reserved 9 c0, Auxiliary Feature Register To access the Debug Feature Register 0 read CP15 withMemory Model Feature Registers C0, Memory Model Feature Register 0, MMFR0 10 Memory Model Feature Register 0 bit functions C0, Memory Model Feature Register 1, MMFR1 11 Memory Model Feature Register 1 bit functions 16 Memory Model Feature Register 1 format C0, Memory Model Feature Register 2, MMFR2 WFIDMB C0, Memory Model Feature Register 3, MMFR3 13 Memory Model Feature Register 3 bit functions3112 Reserved Instruction Set Attributes Registers C0, Instruction Set Attributes Register 0, ISAR014 Instruction Set Attributes Register 0 bit functions 20 Instruction Set Attributes Register 1 format C0, Instruction Set Attributes Register 1, ISAR1 C0, Instruction Set Attributes Register 2, ISAR2 ITEIndicates support for if then instructions 16 Instruction Set Attributes Register 2 bit functions PSRIndicates support for PSR instructions C0, Instruction Set Attributes Register 3, ISAR3 17 Instruction Set Attributes Register 3 bit functionsThumb instruction sets 23 Instruction Set Attributes Register 4 format C0, Instruction Set Attributes Register 4, ISAR4 C0, Instruction Set Attributes Registers 12 c0, Current Cache Size Identification Register18 Instruction Set Attributes Register 4 bit functions 8KB 4KB 3130 Reserved 13 c0, Current Cache Level ID Register 15 c1, System Control Register 14 c0, Cache Size Selection Register AFE 23 System Control Register bit functionsTRE Nmfi = data caching disabled. This is the reset value Enables L1 data cache= data caching enabled = strict alignment fault checking enabled Auxiliary Control Registers C1, Auxiliary Control Register24 Auxiliary Control Register bit functions Axiscuen AxiscenDilsm Deolp Dbwr RsdisDlfo Dnch C15, Secondary Auxiliary Control Register 25 Secondary Auxiliary Control Register bit functions IXC DoofmacsOFC UFC Primary input RMWENRAM1 defines the reset value 17 c1, Coprocessor Access RegisterPrimary input RMWENRAM0 defines the reset value Atcmecc Fault Status and Address Registers C5, Data Fault Status RegisterAll other encodings for these FSR bits are Reserved C5, Instruction Fault Status Register 28 Data Fault Status Register bit functionsTo use the Dfsr read or write CP15 with C5, Auxiliary Fault Status Registers To access the Ifsr read or write CP15 withThere are two auxiliary fault status registers 29 Instruction Fault Status Register bit functions 30 Adfsr and Aifsr bit functions C6, Data Fault Address Register= Atcm = Btcm 19 c6, MPU memory region programming registers C6, Instruction Fault Address Register C6, MPU Region Base Address Registers C6, MPU Region Size and Enable Registers C6, MPU Region Access Control Registers 158 Sub-region disable32 Region Size Register bit functions TEX 33 MPU Region Access Control Register bit functions C6, MPU Memory Region Number Register 34 Access data permission bit encodingUNP 35 MPU Memory Region Number Register bit functions Cache operations Point of Coherency PoCPoint of Unification PoU Set and Way format Invalidate and clean operations Address format 37shows the cache sizes and the resultant bit range for Set36 Functional bits of c7 for Set and Way 37 Widths of the set field for L1 cache sizes Size Set Data Memory Barrier operation Data Synchronization Barrier operation21 c9, Btcm Region Register 38 Functional bits of c7 for address format Bits Field To access the Btcm Region Register, read or write CP15 with 22 c9, Atcm Region Register39 Btcm Region Register bit functions 23 c9, TCM Selection Register To access the Atcm Region Register, read or write CP15 with24 c11, Slave Port Control Register 40 Atcm Region Register bit functions 26 c13, Context ID Register 25 c13, Fcse PID Register312 Reserved RAZ/UNP 27 c13, Thread and Process ID Registers C15, nVAL IRQ Enable Set Register Validation RegistersCcnt overflow IRQ request Ccnt overflow FIQ request C15, nVAL FIQ Enable Set Register C15, nVAL Reset Enable Set Register C15, nVAL Debug Request Enable Set RegisterCcnt overflow reset request Ccnt overflow debug request C15, nVAL IRQ Enable Clear Register 48 nVAL IRQ Enable Clear Register format C15, nVAL FIQ Enable Clear Register 303 Reserved UNP or Sbzp C15, nVAL Reset Enable Clear Register 51 nVAL Debug Request Enable Clear Register format C15, nVAL Debug Request Enable Clear Register 50 nVAL Cache Size Override Register C15, nVAL Cache Size Override Register318 Reserved B0000 4kB B0001 8kB B0011 16kB B0111 32kB B1111 64kB 53 Correctable Fault Location Register cache Correctable Fault Location Register 52 Correctable Fault Location Register cache Build Options Registers To access the Build Options 1 Register, write CP15 withC15, Build Options 1 Register C15, Build Options 2 Register Noicache 55 Build Options 2 RegisterNodcache Atcmes Noie BtcmesNofpu Nompu Noharderrorcach To access the Build Options 2 Register, write CP15 withDcachees Axibusparity Prefetch Unit About the prefetch unit Disabling program flow prediction Branch prediction Configuring the branch predictor Branch predictorIncorrect predictions and correction Return stack Events and Performance Monitor About the events Bit position Update ValueEvent bus interface bit functions Event ETMEXTOUT1 ETMEXTOUT0 Instruction cache access Non-cacheable access on AXI master busBut with different attributes Dual issue case a branch Dual issue case B1, B2, F2 load/store, F2D TCM correctable ECC error reported by prefetch unit Yes TCM correctable ECC error reported by load/store unit Yes About the PMU Performance monitoring registers are described Performance monitoring registers1 c9, Performance Monitor Control Register 2shows how the bit values correspond with the Pmnc Register Pmnc Register bit functions 2 c9, Count Enable Set Register To access the Cntens Register, read or write CP15 with 3 c9, Count Enable Clear RegisterCntens Register bit functions Bits Field Function Cycle counter enable clear To access the Cntenc Register, read or write CP15 with4 c9, Overflow Flag Status Register Cntenc Register bit functions Bits Field Function To access the Flag Register, read or write CP15 with 5shows how the bit values correspond with the Flag Register5 c9, Software Increment Register 6 c9, Performance Counter Selection Register To access the Swincr Register, read or write CP15 withSwincr Register bit functions Bits Field Function 313 Reserved RAZ on reads, Sbzp on writes Increment Counter 7 c9, Cycle Count Register 8 c9, Event Selection RegisterSEL EVTSELx Register bit functions To access the EVTSELx Register, read or write CP15 with 10 c9, User Enable Register 9 c9, Performance Monitor Count RegistersUseren Register bit functions 11 c9, Interrupt Enable Set Register Ccnt overflow interrupt enable10 Intens Register bit functions Bits Field Function 12 c9, Interrupt Enable Clear Register Ccnt overflow interrupt enable bit11 Intenc Register bit functions Bits Field Function To access the Intenc Register, read or write CP15 with Use of the event bus and counters Event bus interface MPU faults on MPU software-accessible registers onMemory Protection Unit Default memory map About the MPUTrue Region base address Memory regionsRegion size Subregions Region attributes Region access permissionsOverlapping regions Region Example of using subregions Example of using regions that overlap TCM regions Background regions Memory types Using memory types ARM DDI 0363E TEX20, C, and B encodings Description Memory Type Shareable? Region attributes 1BB Cacheable memory policies On page 7-2shows the default memory map MPU interaction with memory systemFollowing code is an example of disabling the MPU Background fault Permission fault Alignment fault MPU faultsBackground fault Permission fault On page 4-5shows the CP15 registers that control the MPU MPU software-accessible registers Level One Memory System About the L1 memory system L1 memory system block diagram About the error detection and correction schemes Parity Bit ECC onParity Hard errors Error checking and correctionBit ECC Read-Modify-Write Error correction Correct inlineCorrect-and-retry Faults Fault handlingClasses of fault that can occur are MPU faults External faults Cache and TCM parity and ECC errorsTCM external faults Debug events Fault status informationPrecise and imprecise aborts Abort exceptions Precise abort exceptions Imprecise abort exceptionsUsage models Correctable errors Types of aborts Conditions Source Precise FatalAXI ARM DDI 0363E TCM attributes and permissions About the TCMs Atcm and Btcm configuration TCM internal error detection and correctionHandling TCM parity errors on Handling TCM ECC errors on Handling TCM parity errors Handling TCM ECC errorsTCM arbitration External TCM errors TCM initializationTCM port protocol AXI slave interfaces for TCMs Store buffer About the caches Store buffer merging Cache maintenance operationsStore buffer behavior Store buffer draining Error build options Cache error detection and correction Address decoder faults Handling cache parity errorsCache parity error behavior Value Behavior Cache ECC error behavior Value Behavior Handling cache ECC errors Errors on data cache read Errors on instruction cache readErrors on data cache write Errors on evictions Invalidate all instruction cache Clean data cache by set/way Tag RAM Cache RAM organizationDirty RAM on Data RAM on Tag RAM Data RAM Dirty RAMCache sizes and tag RAM organization Tag RAM organization Organization of a dirty RAM line Nonsequential read operation performed with one RAM access Data RAM sizes without parity or ECC implemented 13 Data cache RAM bits, with parity Description Disabling or enabling all of the caches Cache interaction with memory systemFollowing code is an example of enabling caches 15 Data cache data RAM sizes with ECC Cache size Data RAMs Disabling or enabling error checking Disabling or enabling instruction cacheDisabling or enabling data cache MCR p15 R0, c1 Write System Control Register Internal exclusive monitor Memory types and L1 memory system behavior TCM error events Error detection eventsInstruction-cache error events Data-cache error events ARM DDI 0363E Level Two Interface About the L2 interface AXI master interface 1shows the AXI master interface attributesAttribute Value Comments Outstanding write/read access on different IDs Identifiers for AXI bus accessesOutstanding write accesses with the same ID Write response Memory attributes Eviction bufferArcachem and Awcachem encodings Encoding a Meaning Aruserm and Awuserm encodings Memory system implications for AXI accesses AXI master interface transfers Strongly Ordered and Device transactions onLinefills on Strongly Ordered and Device transactions Restrictions on AXI transfersNon-cacheable Ldrb Address20 Ldrh from Strongly Ordered or Device memory Address30 LDR or LDM that transfers one register LDM5, Strongly Ordered or Device memory Address40 LDM that transfers five registers Strh to Strongly Ordered or Device memory Address20 Strb to Strongly Ordered or Device memory Address40 STR or STM of one register STM of seven registersFirst Wstrbm Linefills Cache line write-back evictionNon-cacheable reads 15 LDR or LDM1 from Non-cacheable Normal memory Address20 14 Ldrh from Non-cacheable Normal memory Address20 Non-cacheable or write-through writes AXI transaction splitting 20 AXI transaction splitting, data in two cache lines Normal write merging Example 9-1 Write merging ARM DDI 0363E AXI slave interface for cache RAMs AXI slave interface TCM parity and ECC support Cache parity and ECC supportAXI slave control 25 AXI slave interface attributes AXI slave characteristics Enabling or disabling AXI slave accesses Accessing RAMs using the AXI slave interface TCM RAM access on Cache RAM access on26 RAM region decode AxUSERS bit One-hot RAM select ARADDRSMSB, see Table TCM RAM access27 TCM chip-select decode Btcm ports RAM selected Cache RAM access Memory map when accessing the cache RAMsThis section contains the following 0010 Bank 0100 1000 Data RAM access31 Cache data RAM bank/address decode Inputs ARADDRS1815 0001 Bank 0010 0100 1000 35 Data format, data cache, with ECC Data bit Description 34 Data format, instruction cache, with ECC Tag RAM access ARM DDI 0363E 43 Dirty register format, with ECC Data bit Description Dirty RAM access ARADDRS1815 = 4b1111 Other examples of accessing cache RAMs About power control on Power management on Power Control About power control Standby mode Run modeDormant mode Shutdown mode Communication to the Power Management Controller Debug state on Cache debug on Debug Debug host Protocol converter Debug target Debug systemsDebug host Protocol converter Halting debug-mode debugging About the debug unitMonitor debug-mode debugging Programming the debug unit All other state information associated with the debug unit Debug register interface 11.3.2 CP14 access permissionsCoprocessor registers Coprocessor registers summary Memory-mapped registers Offset Register Access Mnemonic Description Hex NumberInstruction Mnemonic Description Debug memory-mapped registers Memory addresses for breakpoints and watchpoints Effects of resets on debug registers Power domainsAPB port access permissions Privilege of memory access permission Lock External debug interface access permissions RegistersOther Debug registers Other registers Debug register descriptions Accessing debug registers6shows the CP14 debug register map 11.4.2 CP14 c0, Debug ID Register Debug ID Register functions WRPBRP 11.4.3 CP14 c0, Debug ROM Address Register To use the Debug ID Register, read CP14 c0 withTo use the Debug ROM Address Register, read CP14 c0 with 11.4.4 CP14 c0, Debug Self Address Offset Register Debug Self Address Offset Register functions Debug Self Address Offset Register format 10 Debug Status and Control Register functions 11.4.5 CP14 c1, Debug Status and Control Register Flag is set to 1 on entry to debug state Execute ARM instruction enable bit = disabled, this is the reset valueARM MOE DTR access mode Data Transfer Register 12 Watchpoint Fault Address Register functions Watchpoint Fault Address RegisterVector Catch Register Reserved RAZ SVC Debug State Cache Control Register Bits Field Reset Description ValueInstruction Transfer Register 14 Debug State Cache Control Register functions Debug Run Control Register 15 Debug Run Control Register functions315 Reserved Breakpoint Control Registers Breakpoint Value Registers 17 Breakpoint Control Registers functions Corresponding instruction address breakpoint +0 is accessed18 Meaning of BVR bits BVR2220 Meaning Watchpoint Value Registers Watchpoint Control Registers19 Watchpoint Value Registers functions Bits Description 20 Watchpoint Control Registers functions 11 Watchpoint Control Registers format Operating System Lock Status Register Accessed 21 OS Lock Status Register functions Authentication Status Register Device Power-down and Reset Status Register Device Power-down and Reset Control Register= Dbgnopwrdwn is LOW. This is the reset value 23 Prcr functions 24 Prsr functions 15 Prsr format Processor ID Registers Management registers Claim Registers Claim Tag Set Register27 Claim Tag Set Register functions Bits Field Function 318 Reserved RAZ or Sbzp Claim tag clear Reset value is Lock Access RegisterClaim Tag Clear Register Lock Status Register Device Type Register Debug Identification Registers30 Device Type Register functions Field Size Description 32 Fields in the Peripheral Identification Registers33 Peripheral ID Register 0 functions Bits Value Description 35 Peripheral ID Register 2 functions 34 Peripheral ID Register 1 functions36 Peripheral ID Register 3 functions 37 Peripheral ID Register 4 functions Component Identification Register 10201021 1022 Software debug event Debug events Behavior of the processor on debug events Halting debug eventDebug event priority Watchpoint debug events Debug exception Following sections describe 40shows the values in the link register after exceptionsEffect of debug exceptions on CP15 registers and Wfar Four CP15 registers that record abort information are Avoiding unrecoverable states Privilege on Debug stateEntering debug state 41 Read PC value after debug state entry 41 Read PC value after debug state entry Debug event Behavior of the PC and Cpsr in debug state Executing instructions in debug state Accessing registers and memoryWriting to the Cpsr in debug state Privilege Effect of debug state on non-invasive debug Coprocessor instructionsEffects of debug events on processor registers Exceptions in debug state Imprecise Data Abort Precise Data abortImprecise Data Aborts on entry and exit from debug state Leaving debug state Sets the DSCR1 core restarted flag to This section describes cache debug. It consists Cache debugCache pollution in debug state Cache coherency in debug state Miscellaneous debug signals APB signalsThis section describes the miscellaneous debug signals External debug interface Changing the authentication signals Authentication signals42 Authentication signal restrictions Dbgen a Non-invasive debug permitted Issue an Instruction Synchronization Barrier ISB instruction Example 11-1 Executing an ARM instruction through the ITR Using the debug functionality Debug communications channel Rules for accessing the DCC Debugger access to the DCC Software access to the DCCExample 11-5shows the code for host-to-target data transfer Example 11-4 Target to host data transfer host end This section describes the following operations Programming breakpoints and watchpointsProgramming simple breakpoints and the byte address select Example 11-6 Polling the DCC host end Example 11-7 Setting a simple breakpoint Setting a simple aligned watchpoint Example 11-8 Setting a simple aligned watchpoint Setting a simple unaligned watchpoint 45shows some examples Example 11-9 Setting a simple unaligned watchpointSingle-stepping Not required Debug state entry Example 11-10 Single-stepping off an instructionExample 11-11 Entering debug state Example 11-12 Leaving debug state Debug state exit This section describes the following Accessing registers and memory in debug stateReading and writing registers through the DCC Example 11-13 Reading an ARM register Example 11-15shows the code to read the PC Reading the PC in debug stateReading the Cpsr in debug state Example 11-16shows the code for reading the Cpsr Reading memory Example 11-19 Checking for an abort after memory accessExample 11-18shows the code for reading a byte of memory Example 11-17 Writing the Cpsr Example 11-21 Reading a word of memory Example 11-20 Reading a block of bytes of memory Example 11-23 Reading registers in stall mode Example 11-22 Changing the DTR access modeExample 11-24 Writing registers in stall mode Fast register read/write Example 11-25 Reading a block of words of memory Fast memory read/write Example 11-27 Reading a coprocessor register Accessing coprocessor registers 11-70 Debugging systems with energy management capabilities Emulating power down 11-72 FPU Programmer’s Model About the FPU programmer’s model FPU functionalityAbout the VFPv3-D16 architecture FPU views of the register bank General-purpose registers System registers VFPv3 architecture describes the following system registers1shows the VFP system registers in the Cortex-R4F FPU Fpsid is privileged access only All hardware ID information is privileged access onlyMvfr registers are privileged access only This is a change in VFPv3 compared to VFPv2 Fpscr Register bit functions Floating-Point Status and Control Register, FpscrDNM Rmode LEN Floating-Point Exception Register, FpexcIDE RAZ DNM IXE RAZ UFE OFE DZE IOE IDC Floating-Point Exception Register bit functions Media and VFP Feature Registers, MVFR0 and MVFR1DEX MVFR0 Register bit functions Full denormal arithmetic supported for VFP MVFR1 Register bit functions Full-compliance mode Full-compliance mode Flush-to-zero mode Default NaN modeFlush-to-zero mode Default NaN mode Complete implementation of the Ieee 754 standard Compliance with the Ieee 754 standardIeee 754 standard implementation choices NaN handling Underflow ComparisonsQNaN and SNaN handling CDP Exceptions Integration Test Registers About Integration Test Registers Programming and reading Integration Test Registers Software access using APB Itetmif Register ItctrlItmiscout Itmiscin Processor integration testing 13121110 Performing integration testing Using the Integration Test Registers Itetmif Register bit assignments Bits Name Function Itetmif Register ETM interface Itmiscout Register Miscellaneous Outputs Itmiscin Register Miscellaneous InputsItmiscout Register bit assignments Bits Name Function Bits Name Function Integration Mode Control Register ItctrlDbgrestart Etmextout 7shows the fields of the Itctrl Register Bits Access Reset value Name FunctionRAZ/SBZP Intmode Multiplies on Divide on Branches on Cycle Timings and Interlock Behavior Dual issue on Instruction execution overview About cycle timings and interlock behavior Flag-setting instructions Following sequence where R1 is a Late Reg takes two cyclesConditional instructions Definition of terms Assembler language syntax Instruction Behavior Sequence Register interlock examplesTakes two cycles because there are no register dependencies Takes three cycles because of the result latency of R1 Data processing instructions Cycle counts if destination is not PCCycle counts if destination is the PC Example interlocks ShifterRegister controlled shifts QADD, QDADD, QSUB, and Qdsub instructions SEL Media data-processing Instruction sequence Behavior Sum of Absolute Differences SADResult of the USAD8 instruction USAD8 instruction Umlals Multiplies 14-13 Divide Branches 10 Branch instruction cycle timing behaviorExample instruction Cycles Memory Comments Processor state updating instructions Mode changingAll MRS instructions All MSR instructions to the Spsr 13shows the cycle timing behavior for loads to the PC Single load and store instructions Base register update 13 Cycle timing behavior for loads to the PCExample instruction Cycles Memory Result Comments Latency 14-19 Load and Store Double instructions Register offset, then 3-issue cycles Write-back Load and Store Multiple instructions Correct condition prediction and correct Load Multiples, where the PC is in the register listReturn stack prediction Correct condition prediction and incorrect 14-23 RFE and SRS instructions Clrex Synchronization instructions Some instructions such as cache operations take more cycles Coprocessor instructions Prefetch Abort Undefined Instruction SVC formerly SWI Miscellaneous instructions Floating-point register transfer instructions Blocking and serializingSerializing Bit aligned address Floating-point load/store instructionsNot aligned 2,2 4,5 2,3 Floating-point single-precision data processing instructions Floating-point double-precision data processing instructions Dual issue Dual issue rules Permitted combinations onDual issue rules Dual issue First instruction Second instruction Case Permitted combinations28 Permitted instruction combinations Any single-precision CDPi, excluding Case F2stbMultiply-accumulate instructionso Case F2Db Processor timing on Processor timing parameters on AC Characteristics Processor timing Input port timing parameters Processor timing parametersClock uncertainty 10% Clock uncertainty 50% 3shows the timing parameters for the interrupt input ports 4shows the input timing parameters for the AXI master portClock uncertainty 60% Rreadys 5shows the input timing parameters for the AXI slave port 7shows the input timing parameters for the ETM input ports 6shows the input timing parameters for the debug input ports 8shows the timing parameters for the test input ports Clock uncertainty 65%Clock uncertainty 40% 11shows the timing parameters for the interrupt output ports Output ports timing parameters Write response channel Clock uncertainty 60% 13shows the timing parameters for the AXI slave output ports BRESPS10 Clock uncertainty 45% 16shows the timing parameters for the test output ports Fpidc 18shows the timing parameters for the FPU output signals 15-13 FPU signals on page A-23 Processor Signal Descriptions About the processor signal descriptions AnyFrom any clock Global signals Table A-1 Global signalsSignal Direction Clocking Description Table A-2shows the processor configuration signals Configuration signalsTable A-2 Configuration signals Information Tie High for odd parity Tie LOW for even parity RMWENRAM10b Interrupt signals, including VIC interface signals L2 interface signals Table A-4 AXI master port signals for the L2 interfaceAXI master port Identification tag for the write response signal Identification tag for the write data group of signalsIdentification tag for the read address group of signals Protection signals provide addition information about a bus Table A-5 AXI master port error detection signals AXI master port error detection signalsTable A-6 AXI slave port signals for the L2 interface AXI slave port AXI specification Protection information, privileged/normal access. AWPROT0Protection information, privileged/normal access. ARPROT0 One to 16. a four bit binary value minus one determines ATCM, one hot. AWUSERS30 signal is not part AXI slave port error detection signalsStandard AXI specification Table A-7 AXI slave port error detection signals TCM interface signals Table A-8shows the Atcm port signalsTable A-9shows the B0TCM port signals Table A-10shows the B1TCM port signals Table A-10 B1TCM port signals= DMA Address for B1TCM data RAM B1TCM RAM access is sequentialWrite data for B1TCM data RAM Write parity or ECC code for B1TCM Dual core interface signals Table A-11shows the dual redundant core interface signalsTable A-11 Dual core interface signals Debug interface signals Table A-13shows the debug miscellaneous signalsTable A-12 Debug interface signals Input Tie-off Debug ROM physical address valid Table A-13 Debug miscellaneous signalsInput Tie-off Debug self-address offset Input Tie-off Debug self-address offset valid ETM interface signals Table A-14shows the ETM interface signalsTable A-14 ETM interface signals Test signals Table A-15shows the test signalsTable A-15 Test signals Table A-16shows the Mbist signals Mbist signals Table A-17shows the validation signals Validation signals Table A-18 FPU signals FPU signals ECC scheme selection guidelines on page B-2 ECC Schemes ECC scheme selection guidelines Revisions NCPUHALT removed from timing diagram Added sectionsClarified byte-invariant big-endian format Clarified little-endian format Change Location Table C-1 Differences between issue B and issue C No technical changes Table C-2 Differences between issue C and issue D Abort, and an internal or External Abort GlossarySee also Data Abort, External Abort and Prefetch Abort Base register write-back See Advanced High-performance Bus See also Advanced High-performance BusThat are divisible by four and two respectively See Advanced Microcontroller Bus Architecture Active transfer Active read transactionActive write transaction Completed transfer Read issuing capability Read ID widthWrite ID capability Write ID width See also Beat See also Burst Accessed in parallel during a cache look-up Accesses are expected to be word-alignedSee also Word-invariant Bus See also Dirty See also Clean See Embedded Trace Macrocell By individual implementations An instruction that is architecturally UndefinedOption chosen does not affect software compatibility Precision and the fraction is all zeros See also Halt mode Serviced while normal program execution is suspendedSee Cold reset Result of attempting to access invalid instruction memory See Should Be One Or equal to 1 and is not restricted to being a power of twoSee Should Be Zero See Boundary scan chain Increment of +2 See Debug test access portDestination precision User trap handler is executed Bit for the exception is set Expected behavior for an unaligned accessProcessor-specific. a victim is also known as a cast out A processor Cache terminology diagram