Level One Memory System

8.4.2ATCM and BTCM configuration

The TCM interfaces are configured during implementation and integration.

You can configure the ATCM interface to be removed, and not included in the processor design. If implemented, the ATCM can have only a single port.

You can configure the BTCM interface to:

be removed, and not included in the processor design

have a single BTCM port

have two banked BTCM ports, interleaved on either:

Bit [3] of the address

The most significant bit of the BTCM interface address. This depends on the size of the BTCM.

During implementation, you can configure the ATCM and/or the BTCM to use an error-protection scheme to protect the data stored in the TCM, see TCM internal error detection and correction.

The size of each TCM interface is configured during integration. See the Cortex-R4 and

Cortex-R4F Integration Manual for more information. The permissible TCM sizes are:

0KB

4KB

8KB

16KB

32KB

64KB

128KB

256KB

512KB

1MB

2MB

4MB

8MB.

If the BTCM interface has two ports, the size of the RAM attached to each port is half the total size for the BTCM interface.

The size of the TCM interfaces is visible to software in the TCM Region Registers, see c9, BTCM Region Register on page 4-57and c9, ATCM Region Register on page 4-58.All TCM interface build configuration options can be read from the Build Options Registers, see c15, Build Options 1 Register on page 4-72and c15, Build Options 2 Register on page 4-72.

8.4.3TCM internal error detection and correction

Each TCM interface can be configured with either parity, 32-bit ECC, or 64-bit ECC error schemes. Both the BTCM ports must have the same error scheme. The following sections describe these error schemes:

Handling TCM parity errors on page 8-15

Handling TCM ECC errors on page 8-15.

ARM DDI 0363E

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ARM R4F, r1p3 manual Atcm and Btcm configuration, TCM internal error detection and correction