Programmer’s Model

2.9Acceleration of execution environments

Because the ARMv7-R architecture requires Jazelle® software compatibility, three Jazelle registers are implemented in the processor.

Table 2-7shows the Jazelle register instruction summary and the response to the instructions.

Table 2-7 Jazelle register instruction summary

Register

Instruction

Response

 

 

 

Jazelle ID

MRC p14, 7, <Rd>, c0, c0, 0

Read as zero

 

MCR p14, 7, <Rd>, c0, c0, 0

Ignore writes

 

 

 

Jazelle main configuration

MRC p14, 7, <Rd>, c2, c0, 0

Read as zero

 

MCR p14, 7, <Rd>, c2, c0, 0

Ignore writes

 

 

 

Jazelle OS control

MRC p14, 7, <Rd>, c1, c0, 0

Read as zero

 

MCR p14, 7, <Rd>, c1, c0, 0

Ignore writes

 

 

 

Note

Because no hardware acceleration is present in the processor, when the BXJ instruction is used, the BX instruction is invoked.

ARM DDI 0363E

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ARM R4F, r1p3 manual Acceleration of execution environments