Memory Protection Unit

This section describes:

Memory regions

Overlapping regions on page 7-4

Background regions on page 7-6

TCM regions on page 7-6.

7.1.1Memory regions

Before the MPU is enabled, you must program at least one valid protection region. If you do not do this, the processor will enter a state that only reset can recover.

When the MPU is disabled, no access permission checks are performed, and memory attributes are assigned according to the default memory map. See Table 7-1 on page 7-2.

For more information on how to enable or disable the MPU, see MPU interaction with memory system on page 7-11.

Depending on the implementation, the MPU has a maximum of eight or 12 regions. Using CP15 register c6 you can specify the following for each region:

region base address

region size

subregion enables

region attributes

region access permissions

region enable.

Region base address

The base address defines the start of the memory region. You must align this to a region-sized boundary. For example, if a region size of 8KB is programmed for a given region, the base address must be a multiple of 8KB.

Note

If the region is not aligned correctly, this results in Unpredictable behavior.

Region size

The region size is specified as a 5-bit value, encoding a range of values from 32 bytes, a cache-line length, to 4GB. Table 4-32 on page 4-51shows the encoding.

Subregions

Each region can be split into eight equal sized non-overlapping subregions. An access to a memory address in a disabled subregion does not use the attributes and permissions defined for that region. Instead, it uses the attributes and permissions of a lower priority region or generates a background fault if no other regions overlap at that address. This enables increased protection and memory attribute granularity.

All region sizes between 256 bytes and 4GB support eight subregions. Region sizes below 256 bytes do not support subregions, and the subregion disable field is SBZ/UNP for regions of less than 256 bytes in size.

ARM DDI 0363E

Copyright © 2009 ARM Limited. All rights reserved.

7-3

ID013010

Non-Confidential, Unrestricted Access

 

Page 186
Image 186
ARM R4F, r1p3 manual Memory regions, Region base address, Region size, Subregions